os_cpu_a.s

ucos2400移植的源码。从网上下载供大家分享。

;****************************************************************************************
;*
;*		OS_CPU_A.S -	SAMSUNG S3C2400 ARM BOARD STARTUP ROUTINE
;*
;*		C)	Copyright 2003-3-19 ARM STUDY GROUP (Yoon Gwang-Yoon)
;*			http://arm.cim.co.kr
;*
;*			uC/OS-II ver 2.51 Ported by Lee Chae Won 
;*                      ([e-mail] ; [e-mail]) in 2003.4.20.
;*			http://user.chollian.net/~hebb/
;*
;*			In some part of important core routines, I refered to the sources of
;*			EP-7209 Ports by Mr. Kim Hyo-jun ([e-mail]).
;*		  
;****************************************************************************************
;*
;*	This is the start-up routine of S3C2400 Board, which executes H/W initialization
;*	such as setting PLL, copying the contents of ROM to RAM, initializing C variables,
;*	and jumping to C routines, and so on.
;*
;****************************************************************************************

		GET		HWDEFS.INC	; Init. Settings...

;----------------------------------------------------------------------------------------
;
;   	VECTOR TABLE
;
;----------------------------------------------------------------------------------------

		AREA    |Assembly$$code|, CODE, READONLY
		ENTRY

;----------------------------------------------------------------------------------------
		b		ResetHandler
		ldr		pc, UndefV
		ldr		pc, SWIV
		ldr		pc, PAbortV
		ldr		pc, DAbortV
		ldr		pc, UnusedV
		ldr		pc, IRQV
		ldr		pc, FIQV

;*****************************************************************************
;
; The following is the actual vector table.  It contains the addresses of the
; routines which handle each exception type.
;
;*****************************************************************************
UndefV
		DCD		UndefHandler
SWIV
		DCD		SWIHandler
PAbortV
		DCD		PAbortHandler
DAbortV
		DCD		DAbortHandler
UnusedV
		DCD		UnusedHandler
IRQV
		DCD		IRQHandler
FIQV
		DCD		FIQHandler

;--------------------------------------------------------------------------------
; The undefined instruction handler.
;--------------------------------------------------------------------------------
UndefHandler
		movs    pc, lr

;--------------------------------------------------------------------------------
; The software interrupt handler.
;--------------------------------------------------------------------------------
SWIHandler
		movs    pc, lr

;--------------------------------------------------------------------------------
; The instruction pre-fetch abort handler.
;--------------------------------------------------------------------------------
PAbortHandler
		subs    pc, lr, #4

;--------------------------------------------------------------------------------
; The data abort handler. 
;--------------------------------------------------------------------------------
DAbortHandler
		subs    pc, lr, #8

;--------------------------------------------------------------------------------
; The unused vector handler.  
;--------------------------------------------------------------------------------
UnusedHandler
		movs    pc, lr

;--------------------------------------------------------------------------------
; The IRQ vector handler.  
;--------------------------------------------------------------------------------
IRQHandler
	stmfd	sp!, {r0-r3}

	ldr	r0, =rINTOFFSET
	ldr	r0, [r0]
	cmp	r0,#10        ; Timer0 INT. is requested?
	beq	T0IRQ	     ; If so, go to timer 0 routine.

;
;	if use other IRQ, follow Timer IRQ type...
;	

	ldmfd	sp!,{r0-r3}		
        subs    pc,lr,#4


;------------------------------------------------------------------------
;	Timer0 IRQ Header Part..
;
T0IRQ
	mov	r0, #0x00000400
	ldr	r1, =rSRCPND
	ldr	r2, =rINTPND
	str	r0,[r1]
	str	r0, [r2]		; Timer 0 Pending Clear
	
	mov	r2,sp			; copy IRQ's sp -> r2
	add	sp,sp,#16		; recover IRQ's sp 
	sub	r3,lr,#4		; copy return address -> r3

;............ Added for the sake of preventing interrupt nesting ................
	mrs     r0, spsr		; Copy spsr_irq to r0
	orr	r0, r0, #0x80	; set spsr_irq[7] to '1'
	msr	spsr_cf, r0		; restore spsr_irq
;................................................................................
	
	LDR	r0,=IRQ_2
	MOVS	pc,r0		; At this point, cpsr_svc := spsr_irq...
IRQ_2
	stmfd	sp!,{r3}		; push SVC's pc
	stmfd	sp!,{r4-r12,lr}		; push SVC's r14, r12-r4
	mov	r4,r2
	ldmfd	r4!,{r0-r3}		
	stmfd	sp!,{r0-r3}		; push SVC's r3-r0
	mrs	r5,cpsr			; get cpsr_svc
;............ Added for the sake of preventing interrupt nesting ................
	bic     r5, r5, #0x80		; reset I_bit in order to enable interrupt
	                                ; again when get back to the task again.
;................................................................................

	stmfd	sp!,{r5}		; push SVC's PSR



;
; This IRQ Header is needed for other IRQ Handler
;------------------------------------------------------------------------
	B     	OSTickISR		; Real Body...
	

;--------------------------------------------------------------------------------
; The FIQ vector handler.  
;--------------------------------------------------------------------------------
FIQHandler
		movs    pc, lr

;********************************************************************************
; 	Reset vector of S3C2400 Board... (Starting Point)
;********************************************************************************
ResetHandler

;--------------------------------------------------------------------------------
;	Disable Watch-dog Timer
;--------------------------------------------------------------------------------
		ldr		r0, =rWTCON
		ldr		r1, =0x0         
		str		r1, [r0]
    
;--------------------------------------------------------------------------------
;   Disable all interrupts
;--------------------------------------------------------------------------------
		ldr		r0, =rINTMSK
		ldr		r1, =0xFFFFFFFF
		str		r1, [r0]

;--------------------------------------------------------------------------------
;   init. memory control registers of S3C2400
;--------------------------------------------------------------------------------
		ldr		r0, =SMRDATA
		ldr		r1, =rBWSCON         
		add		r2, r0, #52	
0       
		ldr		r3, [r0], #4    
		str		r3, [r1], #4    
		cmp		r2, r0		
		bne		%B0

;--------------------------------------------------------------------------------
;	Set FCLK = 150.00 MHz, HCLK = PCLK = 75.00 MHz
;--------------------------------------------------------------------------------

		ldr		r0, =rCLKDIVN
		ldr		r1, =0x00000002
		str		r1, [r0]	;--  CLOCK Source (HCLK = 1/2 FCLK, PCLK= 1/2 FCLK)
    


;--------------------------------------------------------------------------------
;	Set PLL lock time
;--------------------------------------------------------------------------------
		ldr		r0, =rLOCKTIME
		ldr		r1, =0xFFFFFF
		str		r1, [r0]
    
;--------------------------------------------------------------------------------
;	Set PLL : MPLL = 150.0MHz
;--------------------------------------------------------------------------------
		ldr		r0, =rMPLLCON          
		ldr		r1, =((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)
		str		r1, [r0]    

;--------------------------------------------------------------------------------
;	LED ON Test Patterns : 0101 --(Delay)--> 1010
;--------------------------------------------------------------------------------

		ldr		r0,=pLED
		ldr		r1,=0x55555555
		strb	r1,[r0]

		ldr 	r1, =0x0	
		ldr 	r2, =0x00030000																			
Delay
		cmp		r1, r2
		ldrne	r3, [r1], #1
		bne		Delay

		ldr		r0,=pLED
		ldr		r1,=0xaaaaaaaa
		strb	r1,[r0]

;--------------------------------------------------------------------------------
; 	Init. Stacks...
;--------------------------------------------------------------------------------
; 	vUndefStack 
;	vAbortStack
;	vUserStack
;--------------------------------------------------------------------------------
; 	Put the ARM processor into IRQ mode.
;--------------------------------------------------------------------------------
		ldr		r0, =0x000000d2
    	msr		cpsr_cf, r0

;--------------------------------------------------------------------------------
; 	Set up the stack pointer for IRQ mode.
;--------------------------------------------------------------------------------
		ldr		r13, =vIRQStackEnd

;--------------------------------------------------------------------------------
; 	Put the ARM processor into FIQ mode.
;--------------------------------------------------------------------------------
		ldr		r0, =0x000000d1
		msr		cpsr_cf, r0

;--------------------------------------------------------------------------------
; 	Set up the stack pointer for FIQ mode.
;--------------------------------------------------------------------------------
		ldr		r13, =vFIQStackEnd

;--------------------------------------------------------------------------------
; 	Put the ARM processor into SVC mode.
;--------------------------------------------------------------------------------
		ldr		r0, =0x000000d3
		msr		cpsr_cf, r0

;--------------------------------------------------------------------------------
; 	Set up the stack pointer. 
;--------------------------------------------------------------------------------
		ldr		r13, =vSVCStackEnd

;--------------------------------------------------------------------------------
; Copy All contents of ROM to RAM for the sake of speed.
;--------------------------------------------------------------------------------
		IMPORT		|Image$$RO$$Limit|		; End point of CODE Area
		IMPORT		|Image$$RW$$Base|		; Start point of RW Area
		IMPORT		|Image$$ZI$$Base|		; End point of RW Area
;--------------------------------------------------------------------------------

		ldr		r0, = pROM_BASE			; Physical ROM start address : 0x0000.0000	
		ldr		r1, = pRAM_BASE			; Physical RAM start address : 0x0c00.0000
		ldr		r2, = |Image$$RO$$Limit|
		ldr		r3, = |Image$$ZI$$Base|
		ldr		r4, = |Image$$RW$$Base|

		sub		r3, r3, r4					; Calculate the size of RW Area