glo_init.c

在TI的C6000系列高速DSP下实现对FLAH芯片的读写

#include <e:\c6x\include\regs.h>
#include <e:\c6x\include\intr.h>     
#include <e:\c6x\include\timer.h>                                  
#include <e:\c6x\include\emif.h>    
#include <e:\c6x\include\dma.h>    
#include <e:\c6x\include\mcbsp.h>
#include <glodef.h>
#pragma CODE_SECTION(Global_Intr,".glo_inrt")
#pragma CODE_SECTION(Global_DMA ,".glo_DMA")
#pragma CODE_SECTION(Global_EMIF,".glo_EMIF")
interrupt void DMA_0(void)	 
{     

	DMA0_SECONDARY_CTRL=0x80;  
    	

	DMA_Status &= 0x7f;     	
}                         
/* Init global interrupt */
void Global_Intr(void)
{                   
	intr_reset();     
	intr_init();	
                            
	                            
	intr_map(CPU_INT8,ISN_DMA_INT0);	/*MAP DMA 0 interrupt to CPU int8*/
	intr_hook(DMA_0,CPU_INT8);
	INTR_ENABLE(CPU_INT8);
	
	
	INTR_ENABLE(CPU_INT_NMI);
}	                                                                          
                 
/*Init global DMA */
void Global_DMA(void)                         
{   	                                 
	/* init global DMA ctrl reg */
	dma_reset();		         	
	dma_global_init(0x0,0x0,0x0,0x2,0x2,0x0,0x0,0x0,0x0);	
}   
/* define global EMIF ctrl */
void Global_EMIF(void)
{                                           
	unsigned int g_ctrl   = GET_REG(EMIF_GCTRL);
	unsigned int ce0_ctrl = GET_REG(EMIF_CE0_CTRL);	
	unsigned int ce1_ctrl = GET_REG(EMIF_CE1_CTRL);	
	unsigned int ce2_ctrl = GET_REG(EMIF_CE2_CTRL);	
	unsigned int ce3_ctrl = GET_REG(EMIF_CE3_CTRL);	
	unsigned int SDRAM_timer = GET_REG(EMIF_SDRAM_REF);
	unsigned int SDRAM_ctrl = GET_REG(EMIF_SDRAM_CTRL);
	
	LOAD_FIELD(&g_ctrl,0x1,SDCEN,1);
	
/*  EMIF CE0 configed as */
	ce0_ctrl=0x40;
/*  EMIF CE1 configed as Flash 128k *8 bits */	
	LOAD_FIELD(&ce1_ctrl, MTYPE_8ROM, MTYPE , MTYPE_SZ );
	LOAD_FIELD(&ce1_ctrl, 5 , READ_SETUP , READ_SETUP_SZ );
	LOAD_FIELD(&ce1_ctrl, 63, READ_STROBE , READ_STROBE_SZ );
	LOAD_FIELD(&ce1_ctrl, 3 , READ_HOLD , READ_HOLD_SZ );
	LOAD_FIELD(&ce1_ctrl, 5 , WRITE_SETUP , WRITE_SETUP_SZ );
	LOAD_FIELD(&ce1_ctrl, 63 , WRITE_STROBE, WRITE_STROBE_SZ);
	LOAD_FIELD(&ce1_ctrl, 3 , WRITE_HOLD , WRITE_HOLD_SZ );
/*  EMIF CE2 configed as SDRAM  */	
	ce2_ctrl =0x30;        
/*  EMIF CE1 configed as VideoOut board FIFO */		
	ce3_ctrl = 0x11510521; /* out board */
/*	ce3_ctrl =0x20e20322;*/
/*  EMIF CE2 configed as SGRAM size fo 16M*/
	LOAD_FIELD(&SDRAM_timer,0X7D0,PERIOD, PERIOD_SZ);
/*	SDRAM_ctrl = 0x07126000;  WT */
 	SDRAM_ctrl = 0x07115000;
	


	emif_init(g_ctrl,ce0_ctrl,ce1_ctrl,ce2_ctrl,ce3_ctrl,SDRAM_ctrl,SDRAM_timer);		
} 
void Global_Init_var()
{
	
	int j;       
}          
void DMA()
{
	DMA0_SRC_ADDR = (unsigned int)0x01400000;
	DMA0_DEST_ADDR = (unsigned int) 0x80008000;
	DMA0_PRIMARY_CTRL=0x03000250; 
	DMA0_SECONDARY_CTRL=0x80;
	DMA0_XFER_COUNTER=0x00000020 ;
	DMA_Status |= 0x80;
	DMA_START(0);
}