cloader.s

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/*****************************************
 Copyright (c) 2001-2002 
 Sigma Designs, Inc. All Rights Reserved
 Proprietary and Confidential
 *****************************************/

/* This is file is part of the Jasper DVD boot loader */


/*
   setup stack and jump to C program
*/

#include "config.h"

.section ".text"
.globl __main_start
__main_start:

	ldr sp, c_stack
	add sp, sp, #STACK_SIZE
	
	b cache_setup
	
c_stack:
	.long __bss_end
c_entry:	
	.long entry

#ifdef QUICKTURN
#warning ***** QUICKTURN HACK ***** Fiq Handling 	
fiq_stub:
	//setup stack
	ldr sp, fiq_stack

	// save registers
	stmdb sp!, {r0-r7,lr}


	// call the C handler	
	ldr r4, fiq_entry
	mov lr, pc
	mov pc, r4

	// restore regs
	ldmia sp!, {r0-r7,lr}

	// return
	subs pc, lr, #4	

fiq_stack:	
	.long (_bss_end__  + 0x100000)
fiq_entry:
	.long fiq_handler

fiq_stub_end:
	
#endif // QUICKTURN
		
/* Set up cache on	*/

cache_setup:
	
	mov	r0, #0
	mcr	p15, 0, r0, c1, c0, 0
#ifdef ENABLE_CACHE
	mcr	p15, 0, r0, c7, c5, 0
	mcr	p15, 0, r0, c7, c6, 0
	mov	r0, #0x17		// Region size = 16MB 
	orr	r0, r0, r0, lsl #8
	mcr	p15, 0, r0, c6, c0, 0
#ifdef ENABLE_CACHE_DATA_WRITEBACK
	mov 	r0, #0xF0		// Cache from 0x04000000 to 0x08000000
#else
	mov	r0, #0x00
#endif	
	orr	r0, r0, r0, lsl #8
	mcr	p15, 0, r0, c2, c0, 0
	mov	r0, #0xF0		// Write buffer from 0x04000000 to 0x08000000
	mcr	p15, 0, r0, c3, c0, 0
	mov	r0, #0xFF
	orr	r0, r0, r0, lsl #8
	mcr	p15, 0, r0, c4, c0, 0
	mcr	p15, 0, r0, c5, c0, 0

	mov	r0, #0x1000
#ifdef ENABLE_CACHE_DATA
	orr 	r0, r0, #0x7 @ I+D cache on =7  , I cache only =1. does not work with 5 (D cache- writetrough.
#else
	orr	r0, r0, #0x1
#endif

	mcr	p15, 0, r0, c1, c0, 0
#endif	

	nop
	nop
	nop
	nop
	nop

#ifdef QUICKTURN
#warning ***** QUICKTURN HACK ***** Install Bkpt Handler 	
install_bkpt_handler:
	// remap now
	mov 	r2, #0x00500000
	ldr	r1, [r2, #0x0C]
	orr	r1, r1, #0x1
	str	r1, [r2, #0x0C]

	// setup the FIQ vector
	adr r0, fiq_stub
	ldmia r0, {r1-r12}
	mov r0, #0x1C
	stmia r0, {r1-r12}

/*	
	// Set up pio1 for bkpt interrupt
	mov r0, #0x00500000
	orr r0, r0, #0x0600
	
	// Set Direction Input for pios 0-7
	mvn r1, #0xFF
	str r1, [r0, #0x8]
	// Invert Polarity for pios 0-7
	mvn r1, #0xFF00
	str r1, [r0, #0xC]
	// Clears pio interrupt (0-7)
	str r1, [r0, #0x0]
	// Enable pio interrupt (0-7)
	str r1, [r0, #0x10]
*/	
	// enable FIQ	
    mrs r0, CPSR
    bic r0, r0, #0x40
    msr CPSR_c, r0

	// enable int controller
	mov r0, #0x00500000
	orr r0, r0, #0x200
	
	mov r1, #0x20
	str r1, [r0, #0x10]	// set pio0 type to FIQ
	orr r1, r1, #0x80000000	// global irq enable
	str r1, [r0, #0x24]	// enable pio0 int

#endif
	
go_main:
	ldr r4, c_entry
	mov r0, #0
	mov lr, pc
	mov pc, r4
	
	mov r4, r0

/* cache flush before jump	*/

	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 0
	mov	r0, #0
	mcr	p15, 0, r0, c7, c6, 0	
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0

/* cache disable */
			
	mov	r0, #0
	mcr	p15, 0, r0, c1, c0, 0

	nop
	nop
	nop
	nop
	nop		

jump:	
	
	mov r0, #0
	mov pc, r4