jasper.h

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//------------------------------------------------------
// SPI/I2S_DMA REGISTERs 0x0050_1700
//------------------------------------------------------
#define		JASPER_SPI_I2S_DMA_BASE		0x00501700

#define		SPI_I2S_DMA_CTRL_REG		0x0
#define		SPI_I2S_DMA_BASE_ADD_REG	0x4
#define		SPI_I2S_DMA_SIZE_REG		0x8
#define		SPI_I2S_DMA_WR_PTR_REG		0xC
#define		SPI_I2S_DMA_RD_PTR_REG		0x10
#define		SPI_I2S_DMA_TRSH_REG		0x14
#define		SPI_I2S_DMA_INT_EN_REG		0x18
#define		SPI_I2S_DMA_INT_REG			0x1C
#define		SPI_I2S_DMA_INT_POLL_REG	0x20
#define		SPI_I2S_DMA_INTER_FIFO_REG	0x24
#define		SPI_I2S_DMA_CNT_REG			0x28

//------------------------------------------------------
// SPI REGISTERs 0x0050_1800
//------------------------------------------------------
#define		JASPER_SPI_BASE			0x00501800

#define		SPI_CNTR			0x0
#define		SPI_REC_COUNTER			0x4
#define		SPI_INT_EN			0x8
#define		SPI_INT_STATUS			0xC
#define		SPI_ERROR_CNT			0x10


//------------------------------------------------------
// QUASAR PM/DM AREA
//------------------------------------------------------
#define		JASPER_QUASAR_BASE		0x00600000

#define		QUASAR_MAP_AREA			0x00600000
#define		QUASAR_PM_START			0x00600000
#define		QUASAR_PM_SIZE			0x00002000
#define		QUASAR_DM_START			0x00604000
#define		QUASAR_DM_SIZE		   	0x00002000

//------------------------------------------------------
// QUASAR DRAM CONTROLLER
//------------------------------------------------------

#define		QUASAR_DRAM_CFG			0x00007000
#define		QUASAR_DRAM_FIFOSIZE0		0x00007004
#define		QUASAR_DRAM_FIFOSIZE1		0x00007008
#define		QUASAR_DRAM_CASDELAY		0x0000700C
#define		QUASAR_DRAM_PLLCONTROL		0x00007010
#define		QUASAR_DRAM_TK0			0x00007014
#define		QUASAR_DRAM_TK1			0x00007018
#define		QUASAR_DRAM_TK2			0x0000701C
#define		QUASAR_DRAM_STARTUP0		0x00007020
#define		QUASAR_DRAM_STARTUP1		0x00007024
#define		QUASAR_DRAM_AC3_BASE		0x00007028
#define		QUASAR_DRAM_FIFOSIZE2		0x0000702C
#define		QUASAR_DRAM_PORTMUX		0x00007030

//------------------------------------------------------
// QUASAR <-> HOST INTERFACE ( DMA ENGINES )
//------------------------------------------------------

#define		QUASAR_H2Q_READ_ADDRESS_LO	0x00007F80	//0xFE0
#define		QUASAR_H2Q_READ_ADDRESS_HI	0x00007F84	//0xFE1
#define		QUASAR_H2Q_READ_CONTER		0x00007F88	//0xFE2
#define		QUASAR_H2Q_READ_MASTER_ENABLE	0x00007F8C	//0xFE3
#define		QUASAR_H2Q_INT_MASK		0x00007F90	//0xFE4
#define		QUASAR_H2Q_INT			0x00007F94	//0xFE5
#define		QUASAR_H2Q_INT_STATUS		0x00007F98	//0xFE6

#define		QUASAR_Q2H_WRITE_ADDRESS_LO	0x00007FA0	//0xFE8
#define		QUASAR_Q2H_WRITE_ADDRESS_HI	0x00007FA4	//0xFE9
#define		QUASAR_Q2H_WRITE_CONTER		0x00007FA8	//0xFEA
#define		QUASAR_Q2H_WRITE_MASTER_ENABLE	0x00007FAC	//0xFEB
#define		QUASAR_Q2H_INT_MASK		0x00007FB0	//0xFEC
#define		QUASAR_Q2H_INT			0x00007FB4	//0xFED
#define		QUASAR_Q2H_INT_STATUS		0x00007FB8	//0xFEE

#define		QUASAR_OSD_SOURCE_ADDRESS_LO	0x00007980	//0xE60
#define		QUASAR_OSD_SOURCE_ADDRESS_HI	0x00007984	//0xE61
#define		QUASAR_OSD_SOURCE_COUNTER	0x00007988	//0xE62
#define		QUASAR_OSD_SOURCE_MUX_ENABLE	0x0000798C	//0xE63
#define		QUASAR_OSD_INT_MASK		0x00007990	//0xE64
#define		QUASAR_OSD_INT			0x00007994	//0xE65
#define		QUASAR_OSD_INT_STATUS		0x00007998	//0xE66

//------------------------------------------------------
// QUASAR Local Bus Controller (LBC)
//------------------------------------------------------

#define QUASAR_LBC_CONFIG0			0x00007900 //0x1E40
#define QUASAR_LBC_CONFIG1			0x00007904 //0x1E41
#define QUASAR_LBC_WRITE_FIFO0_ACCESS		0x00007908 //0x1E42
#define QUASAR_LBC_WRITE_FIFO0_CNT		0x0000790C //0x1E43
#define QUASAR_LBC_READ_FIFO0_ACCESS		0x00007910 //0x1E44
#define QUASAR_LBC_READ_FIFO0_CNT		0x00007914 //0x1E45
#define QUASAR_LBC_READ_FIFO1_ACCESS		0x00007918 //0x1E46
#define QUASAR_LBC_READ_FIFO1_CNT		0x0000791C //0x1E47
#define QUASAR_LBC_WRITE_ADDR			0x00007920 //0x1E48
#define QUASAR_LBC_WRITE_DATA			0x00007924 //0x1E49
#define QUASAR_LBC_READ_ADDR		        0x00007928 //0x1E4a
#define QUASAR_LBC_READ_DATA		        0x0000792C //0x1E4b
#define QUASAR_LBC_BURST_XFER_CTRL		0x00007930 //0x1E4c
#define QUASAR_LBC_STATUS			0x00007934 //0x1E4d
#define QUASAR_LBC_INTERRUPT			0x00007938 //0x1E4e
#define QUASAR_LBC_PGIO				0x0000793C //0x1E4f

//------------------------------------------------------
// PIO COMMAND DEFINITIONS
//------------------------------------------------------
// IN/OUTPUT PIO direction
#define		PIO_OUTPUT_BIT0			0x00010001
#define		PIO_OUTPUT_BIT1			0x00020002
#define		PIO_OUTPUT_BIT2			0x00040004
#define		PIO_OUTPUT_BIT3			0x00080008
#define		PIO_OUTPUT_BIT4			0x00100010
#define		PIO_OUTPUT_BIT5			0x00200020
#define		PIO_OUTPUT_BIT6			0x00400040
#define		PIO_OUTPUT_BIT7			0x00800080
#define		PIO_OUTOUT_ALL16BITS		0xFFFFFFFF
// Set DATA to the PIO OUTPUT pin
#define		PIO_DATA_BIT0			0x00010001
#define		PIO_DATA_BIT1			0x00020002
#define		PIO_DATA_BIT2			0x00040004
#define		PIO_DATA_BIT3			0x00080008
#define		PIO_DATA_BIT4			0x00100010
#define		PIO_DATA_BIT5			0x00200020
#define		PIO_DATA_BIT6			0x00400040
#define		PIO_DATA_BIT7			0x00800080

#define		PIO_EN_SET_BIT7			0x00800000
#define		PIO_EN_SET_BIT6			0x00400000
#define		PIO_EN_SET_BIT5			0x00200000
#define		PIO_EN_SET_BIT4			0x00100000
#define		PIO_EN_SET_BIT3			0x00080000
#define		PIO_EN_SET_BIT2			0x00040000
#define		PIO_EN_SET_BIT1			0x00020000
#define		PIO_EN_SET_BIT0			0x00010000
#define		PIO_EN_ALL16_BITS		0xFFFF0000
#define		PIO_EN_BITS15to8		0xFF000000
#define		PIO_EN_BITS7to0			0x00FF0000

//------------------------------------------------------
// INT CTRL COMMAND DEFINITIONS
//------------------------------------------------------
#define     ENABLE_TIMER0_INT			0x00000001
#define     ENABLE_TIMER1_INT			0x00000002
#define     ENABLE_PIO0_INT			0x00000020
#define     ENABLE_PIO1_INT			0x00000040

#define		GLOBAL_INT_ENABLE		0x80000000

#define		MAX_INT				0x00800000
#define		Q2H_LOC_INT			0x00400000
#define		Q2H_RISC_INT			0x00200000
#define		SPI_INT				0x00100000
#define		SPI_I2S_DMA_INT			0x00080000
#define		I2S_INT				0x00040000
#define		RTC_INT				0x00020000
#define		Q2P_INT				0x00010000
#define		P2Q_DMA_INT			0x00008000
#define		OSD_DMA_INT			0x00004000
#define		FIP_INT				0x00002000
#define		IDE_DMA_INT			0x00001000
#define		IDE_INT				0x00000800
#define		DVD_DMA_INT			0x00000400
#define		DVD_INT				0x00000200
#define		I2CS_INT			0x00000100
#define		I2CM_INT			0x00000080
#define		PIO1_INT			0x00000040
#define		PIO0_INT			0x00000020
#define		UART1_INT			0x00000008
#define		UART0_INT			0x00000004
#define		WDTIMER_INT			0x00000002
#define		TIMER1_INT			0x00000002
#define		TIMER0_INT			0x00000001

#define		JASPER_SC_VALID_INT		0x007FFFEF

//------------------------------------------------------
// INT CTRL COMMAND DEFINITIONS II for J_IRQCTRL.c
//------------------------------------------------------
#define ENABLE_INT_GLOBAL		0x80000000		//INT_ENABLE command

#define ENABLE_INT_TIMER0		0x80000001		//INT_ENABLE command
#define ENABLE_INT_WDTIMER		0x80000002		//INT_ENABLE command
#define ENABLE_INT_UART_1		0x80000004		//INT_ENABLE command
#define ENABLE_INT_UART_2		0x80000008		//INT_ENABLE command

#define ENABLE_INT_PIO			0x80000020		//INT_ENABLE command
#define ENABLE_INT_PIO1			0x80000040		//INT_ENABLE command
#define ENABLE_INT_I2C_MASTER		0x80000080		//INT_ENABLE command

#define ENABLE_INT_I2C_SLAVE		0x80000100		//INT_ENABLE command
#define ENABLE_INT_DVD			0x80000200		//INT_ENABLE command
#define ENABLE_INT_DVD_DMA		0x80000400		//INT_ENABLE command
#define ENABLE_INT_IDE			0x80000800		//INT_ENABLE command

#define ENABLE_INT_IDE_DMA		0x80001000		//INT_ENABLE command
#define ENABLE_INT_FIP			0x80002000		//INT_ENABLE command
#define ENABLE_INT_OSD_DMA		0x80004000		//INT_ENABLE command
#define ENABLE_INT_H2Q_DMA		0x80008000		//INT_ENABLE command

#define ENABLE_INT_Q2H_DMA		0x80010000		//INT_ENABLE command
#define ENABLE_INT_RTC			0x80020000		//INT_ENABLE command
#define ENABLE_INT_I2S			0x80040000		//INT_ENABLE command
#define ENABLE_INT_I2S_DMA		0x80080000		//INT_ENABLE command

#define ENABLE_INT_SPI			0x80100000		//INT_ENABLE command
#define ENABLE_INT_Q2H_RISC		0x80200000		//INT_ENABLE command
#define ENABLE_INT_Q2H_LOC		0x80400000		//INT_ENABLE command

#define DISABLE_INT_GLOBAL		0x7FFFFFFF		//INT_ENABLE command
#define DISABLE_INT_UART_1		0xFFFFFFFB		//INT_ENABLE command
#define DISABLE_INT_UART_2		0xFFFFFFF7		//INT_ENABLE command
#define DISABLE_INT_ALL			0x10000000		//INT_ENABLE command

//------------------------------------------------------
//SYSTEM CTRL COMMAND DEFINITIONS
//------------------------------------------------------
#define		SYSCTRL_CMD_RESET_TIMER		0x00000001	// Bit 0
#define		SYSCTRL_CMD_RESET_INTCTRL	0x00000002	// Bit 1
#define		SYSCTRL_CMD_RESET_UART0		0x00000004	// Bit 2
#define		SYSCTRL_CMD_RESET_UART1		0x00000008	// Bit 3
#define		SYSCTRL_CMD_RESET_MAC		0x00000010	// Bit 4
#define		SYSCTRL_CMD_RESET_PIO0		0x00000020	// Bit 5
#define		SYSCTRL_CMD_RESET_PIO1		0x00000040	// Bit 6
#define		SYSCTRL_CMD_RESET_I2CM		0x00000080	// Bit 7

#define		SYSCTRL_CMD_RESET_I2CS		0x00000100	// Bit 8
#define		SYSCTRL_CMD_RESET_DVD		0x00000200	// Bit 9
#define		SYSCTRL_CMD_RESET_DVD_DMA	0x00000400	// Bit10
#define		SYSCTRL_CMD_RESET_IDE		0x00000800	// Bit11
#define		SYSCTRL_CMD_RESET_IDE_DMA	0x00001000	// Bit12
#define		SYSCTRL_CMD_RESET_FIP		0x00002000	// Bit13
#define		SYSCTRL_CMD_RESET_OSD_DMA	0x00004000	// Bit14
#define		SYSCTRL_CMD_RESET_H2Q_DMA	0x00008000	// Bit15

#define		SYSCTRL_CMD_RESET_Q2H_DMA	0x00010000	// Bit16
#define		SYSCTRL_CMD_RESET_RTC		0x00020000	// Bit17
#define		SYSCTRL_CMD_RESET_I2S		0x00040000	// Bit18
#define		SYSCTRL_CMD_RESET_I2S_DMA	0x00080000	// Bit19
#define		SYSCTRL_CMD_RESET_SPI		0x00100000	// Bit20
#define		SYSCTRL_CMD_RESET_SLAVE		0x00200000	// Bit21
#define		SYSCTRL_CMD_RESET_3		0x00400000	// Bit22
#define		SYSCTRL_CMD_RESET_4		0x00800000	// Bit23

#define		SYSCTRL_CMD_RESET_5		0x01000000	// Bit24
#define		SYSCTRL_CMD_RESET_6		0x02000000
#define		SYSCTRL_CMD_RESET_7		0x03000000
#define		SYSCTRL_CMD_RESET_8		0x04000000
#define		SYSCTRL_CMD_RESET_10		0x10000000
#define		SYSCTRL_CMD_RESET_11		0x20000000
#define		SYSCTRL_CMD_RESET_Q4		0x40000000	// Bit30
#define		SYSCTRL_CMD_RESET_ALL		0x80000000	// Bit31