state_m.v

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/* State machine design for Quartus tutorial Project */

module state_m ( clk, reset, newt, sel, next, first);

  // Port Declaration
input clk, reset, newt;
output next, first;
output [1:0]sel;

  // Wire Declaration
reg next, first;
reg [1:0] sel;
reg [2:0] filter;

parameter idle = 0, tap1 = 1, tap2 = 2, tap3 = 3, tap4 = 4;

always
begin
	case (filter)
		idle: begin
				sel = 0;
				next = 0;
				first = 0;
			  end

		tap1: begin
				sel = 0;
				next=0;
				first = 1;
			  end

		tap2: begin
				sel = 1;
				next=0;
				first = 0;
			  end

		tap3: begin
				sel = 2;
				next=0;
				first=0;
			  end

		tap4: begin
				sel = 3;
				next = 1;
				first=0;
			   end
	endcase
end


always @(posedge clk or posedge reset)
begin
	if (reset)
		filter = idle;
	else
		case (filter)
			idle: begin
				if (newt)
					filter = tap1;
				  end
				
			tap1: begin
					filter = tap2;
				  end

			tap2: begin
					filter = tap3;
				  end

			tap3: begin
					filter = tap4;
				  end

			tap4: begin
					if (newt)
						filter = tap1;
					else
						filter = idle;
				   end
		endcase	

end		
endmodule