taps.v

来自「Altare公司训练新人的练习题下载.rar FPGA/CPLD」· Verilog 代码 · 共 45 行

/* Taps design for Quartus Tutorial */

module taps (clk, newt, reset, d, sel, x, xn, xn_1, xn_2, xn_3);

// Port Declaration
input clk, newt, reset;
input [1:0] sel;
input [7:0] d;
output [7:0] x, xn, xn_1, xn_2, xn_3;

// Wire Declaration
reg [7:0] x, xn, xn_1, xn_2, xn_3;

// Register element
always @(posedge clk or posedge reset)
begin
if (reset)
	begin
		xn = 0;
		xn_1 = 0;
		xn_2 = 0;
		xn_3 = 0;
	end
else if (newt)
	begin
		xn_3 = xn_2;
		xn_2 = xn_1;
		xn_1 = xn;
		xn = d;
	end
end

// Mux element

always @(sel or xn or xn_1 or xn_2 or xn_3)
case (sel)
2'b 00: x = xn;
2'b 01: x = xn_1;
2'b 10: x = xn_2;
2'b 11: x = xn_3;
default: x = 8'b X;
endcase

endmodule