lab3.tcl

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proc prepare_project {input_name} {

	puts "Deleting old project files"
	file delete $input_name.psf
	file delete $input_name.quartus
	file delete $input_name.csf
	file delete -force db

#	Create project
	set status [project create $input_name]
	if {[string match $input_name $status]} {
		puts "Created project $input_name"
	}

#	Open project
	set status [project open $input_name]
	if {[string match $input_name $status]} {
		puts "Opened project $input_name"
	}

#	Create cmp
	if {[project cmp_exists $input_name] != 1} {
		project create_cmp $input_name
	}

#	Set current cmp
	set status [project set_active_cmp $input_name]
	if {[string match "cap" $status]} {
		puts "Created compiler point $input_name"
	}

#	Add Compiler assignments
	set status [cmp add_assignment $input_name "" "" DEVICE AUTO]
	if {[string match "assignment made" $status]} {
		puts "Device assignment added"
	}

	set status [cmp add_assignment "" "" "" ROOT "|$input_name"]
	if {[string match "assignment made" $status]} {
		puts "Root assignment added"
	}

#	Add file to project
	set status [project add_assignment "" "" "" "" SOURCE_FILE $input_name.edf]
	if {[string match "project assignment added" $status]} {
		puts "Source file assignment added"
	}

#	Add EDA settings to project
	set status [project add_assignment "" "$input_name" "" "" EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "FPGA EXPRESS"]
	if {[string match "project assignment added" $status]} {
		puts "EDA Synthesis tool assignment added"
	}

	set status [project add_assignment "" "eda_design_synthesis" "" "" EDA_LAUNCH_TOOL "OFF"]
	if {[string match "project assignment added" $status]} {
		puts "EDA Launch tool assignment added"
	}

	set status [project add_assignment "" "eda_design_synthesis" "" "" EDA_INPUT_GND "GND"]
	if {[string match "project assignment added" $status]} {
		puts "EDA Input GND assignment added"
	}

	set status [project add_assignment "" "eda_design_synthesis" "" "" EDA_INPUT_VCC "VDD"]
	if {[string match "project assignment added" $status]} {
		puts "EDA Input VCC assignment added"
	}

	set status [project add_assignment "" "eda_design_synthesis" "" "" EDA_USE_LMF "$input_name.lmf"]
	if {[string match "project assignment added" $status]} {
		puts "EDA LMF assignment added"
	}

}

proc compile {} {

#	Start Compiling
	set status [cmp start true]
	if {$status == 1} {
		puts "Compilation started"
	}
	while {[cmp is_running]} {
		after 10
		FlushEventQueue
	}
}

prepare_project micro
compile
project close
exit