lab7.tcl

Altare公司训练新人的练习题下载.rar FPGA/CPLD

proc compile {prjct} {
	project set_active_cmp $prjct
	cmp start "Compile"
	while {[cmp is_running]} {
		 after 10
		 FlushEventQueue
	}
}

# Edit this next line to set labdir to your <lab install dir>
set labdir {d:/training/quartus}

set name dff4
set extension tdf
set device_name EP20K100TC144-3

if {[file exists $labdir/reference_design/iq_modulation/$name.$extension] == 0} {
	puts "Couldn't find the $name.$extension file in the \
		$labdir/reference_design/iq_modulation directory.  Check your labdir variable."  
} else {
	if {[project exists $labdir/reference_design/iq_modulation/$name] == 0} {
		puts "Project does not exist.  Creating a new project."
		project create $labdir/reference_design/iq_modulation/$name
	}

	puts "Opening $name project."
	project open $labdir/reference_design/iq_modulation/$name

	puts "Adding source file $name.tdf." 
	project add_assignment  "" "" "" "" SOURCE_FILE $name.tdf

	if {[project cmp_exists $name] == 0}	{
		puts "No compilation focus.  Creating $name compilation focus."
		project create_cmp $name
	}
	puts "Making $name the active compiler setting"
	project set_active_cmp $name

	puts "Assigning device $device_name to project $name."
	cmp add_assignment $name "" "" device $device_name

	puts "Compiling design $name."
	compile $name
}