lab2.vqm

Altare公司训练新人的练习题下载.rar FPGA/CPLD

assign result_0_and2_0_and2[1] = result_0_and2_0_and2_1;
assign result_0_and2_0_and2[0] = result_0_and2_0_and2_0;
endmodule /* adder */

module regis16 (
  result_15,
  result_14,
  result_13,
  result_12,
  result_11,
  result_10,
  result_9,
  result_8,
  result_7,
  result_6,
  result_5,
  result_4,
  result_3,
  result_2,
  result_1,
  result_0,
  sum_1_add15,
  sum_1_add14,
  sum_1_add13,
  sum_1_add12,
  sum_1_add11,
  sum_1_add10,
  sum_1_add9,
  sum_1_add8,
  sum_1_add7,
  sum_1_add6,
  sum_1_add5,
  sum_1_add4,
  sum_1_add3,
  sum_1_add2,
  sum_1_add1,
  clken_i,
  regclr_i,
  clk,
  sum_1_add0
);
output result_15;
output result_14;
output result_13;
output result_12;
output result_11;
output result_10;
output result_9;
output result_8;
output result_7;
output result_6;
output result_5;
output result_4;
output result_3;
output result_2;
output result_1;
output result_0;
input sum_1_add15;
input sum_1_add14;
input sum_1_add13;
input sum_1_add12;
input sum_1_add11;
input sum_1_add10;
input sum_1_add9;
input sum_1_add8;
input sum_1_add7;
input sum_1_add6;
input sum_1_add5;
input sum_1_add4;
input sum_1_add3;
input sum_1_add2;
input sum_1_add1;
input clken_i;
input regclr_i;
input clk;
input sum_1_add0;
wire result_15 ;
wire result_14 ;
wire result_13 ;
wire result_12 ;
wire result_11 ;
wire result_10 ;
wire result_9 ;
wire result_8 ;
wire result_7 ;
wire result_6 ;
wire result_5 ;
wire result_4 ;
wire result_3 ;
wire result_2 ;
wire result_1 ;
wire result_0 ;
wire sum_1_add15 ;
wire sum_1_add14 ;
wire sum_1_add13 ;
wire sum_1_add12 ;
wire sum_1_add11 ;
wire sum_1_add10 ;
wire sum_1_add9 ;
wire sum_1_add8 ;
wire sum_1_add7 ;
wire sum_1_add6 ;
wire sum_1_add5 ;
wire sum_1_add4 ;
wire sum_1_add3 ;
wire sum_1_add2 ;
wire sum_1_add1 ;
wire clken_i ;
wire regclr_i ;
wire clk ;
wire sum_1_add0 ;
wire [15:0] result;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @3:9
  apex20k_lcell out_reg_0_ (
	.regout(result[0]),
	.clk(clk),
	.dataa(sum_1_add0),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_0_.operation_mode="normal";
defparam out_reg_0_.output_mode="reg_only";
defparam out_reg_0_.packed_mode="false";
defparam out_reg_0_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_1_ (
	.regout(result[1]),
	.clk(clk),
	.dataa(sum_1_add1),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_1_.operation_mode="normal";
defparam out_reg_1_.output_mode="reg_only";
defparam out_reg_1_.packed_mode="false";
defparam out_reg_1_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_2_ (
	.regout(result[2]),
	.clk(clk),
	.dataa(sum_1_add2),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_2_.operation_mode="normal";
defparam out_reg_2_.output_mode="reg_only";
defparam out_reg_2_.packed_mode="false";
defparam out_reg_2_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_3_ (
	.regout(result[3]),
	.clk(clk),
	.dataa(sum_1_add3),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_3_.operation_mode="normal";
defparam out_reg_3_.output_mode="reg_only";
defparam out_reg_3_.packed_mode="false";
defparam out_reg_3_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_4_ (
	.regout(result[4]),
	.clk(clk),
	.dataa(sum_1_add4),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_4_.operation_mode="normal";
defparam out_reg_4_.output_mode="reg_only";
defparam out_reg_4_.packed_mode="false";
defparam out_reg_4_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_5_ (
	.regout(result[5]),
	.clk(clk),
	.dataa(sum_1_add5),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_5_.operation_mode="normal";
defparam out_reg_5_.output_mode="reg_only";
defparam out_reg_5_.packed_mode="false";
defparam out_reg_5_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_6_ (
	.regout(result[6]),
	.clk(clk),
	.dataa(sum_1_add6),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_6_.operation_mode="normal";
defparam out_reg_6_.output_mode="reg_only";
defparam out_reg_6_.packed_mode="false";
defparam out_reg_6_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_7_ (
	.regout(result[7]),
	.clk(clk),
	.dataa(sum_1_add7),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_7_.operation_mode="normal";
defparam out_reg_7_.output_mode="reg_only";
defparam out_reg_7_.packed_mode="false";
defparam out_reg_7_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_8_ (
	.regout(result[8]),
	.clk(clk),
	.dataa(sum_1_add8),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_8_.operation_mode="normal";
defparam out_reg_8_.output_mode="reg_only";
defparam out_reg_8_.packed_mode="false";
defparam out_reg_8_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_9_ (
	.regout(result[9]),
	.clk(clk),
	.dataa(sum_1_add9),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_9_.operation_mode="normal";
defparam out_reg_9_.output_mode="reg_only";
defparam out_reg_9_.packed_mode="false";
defparam out_reg_9_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_10_ (
	.regout(result[10]),
	.clk(clk),
	.dataa(sum_1_add10),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_10_.operation_mode="normal";
defparam out_reg_10_.output_mode="reg_only";
defparam out_reg_10_.packed_mode="false";
defparam out_reg_10_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_11_ (
	.regout(result[11]),
	.clk(clk),
	.dataa(sum_1_add11),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_11_.operation_mode="normal";
defparam out_reg_11_.output_mode="reg_only";
defparam out_reg_11_.packed_mode="false";
defparam out_reg_11_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_12_ (
	.regout(result[12]),
	.clk(clk),
	.dataa(sum_1_add12),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_12_.operation_mode="normal";
defparam out_reg_12_.output_mode="reg_only";
defparam out_reg_12_.packed_mode="false";
defparam out_reg_12_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_13_ (
	.regout(result[13]),
	.clk(clk),
	.dataa(sum_1_add13),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_13_.operation_mode="normal";
defparam out_reg_13_.output_mode="reg_only";
defparam out_reg_13_.packed_mode="false";
defparam out_reg_13_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_14_ (
	.regout(result[14]),
	.clk(clk),
	.dataa(sum_1_add14),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_14_.operation_mode="normal";
defparam out_reg_14_.output_mode="reg_only";
defparam out_reg_14_.packed_mode="false";
defparam out_reg_14_.lut_mask="aaaa";
// @3:9
  apex20k_lcell out_reg_15_ (
	.regout(result[15]),
	.clk(clk),
	.dataa(sum_1_add15),
	.aclr(regclr_i),
	.ena(clken_i)
);
defparam out_reg_15_.operation_mode="normal";
defparam out_reg_15_.output_mode="reg_only";
defparam out_reg_15_.packed_mode="false";
defparam out_reg_15_.lut_mask="aaaa";
assign result_15 = result[15];
assign result_14 = result[14];
assign result_13 = result[13];
assign result_12 = result[12];
assign result_11 = result[11];
assign result_10 = result[10];
assign result_9 = result[9];
assign result_8 = result[8];
assign result_7 = result[7];
assign result_6 = result[6];
assign result_5 = result[5];
assign result_4 = result[4];
assign result_3 = result[3];
assign result_2 = result[2];
assign result_1 = result[1];
assign result_0 = result[0];
endmodule /* regis16 */

module cnter (
  sum_1,
  sum_0,
  G_67,
  start,
  clk
);
output sum_1;
output sum_0;
input G_67;
input start;
input clk;
wire sum_1 ;
wire sum_0 ;
wire G_67 ;
wire start ;
wire clk ;
wire [1:0] sum;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @6:8
  apex20k_lcell sum_0_ (
	.regout(sum[0]),
	.clk(clk),
	.dataa(sum[0]),
	.aclr(start)
);
defparam sum_0_.operation_mode="normal";
defparam sum_0_.output_mode="reg_only";
defparam sum_0_.packed_mode="false";
defparam sum_0_.lut_mask="5555";
// @6:8
  apex20k_lcell sum_1_ (
	.regout(sum[1]),
	.clk(clk),
	.dataa(G_67),
	.aclr(start)
);
defparam sum_1_.operation_mode="normal";
defparam sum_1_.output_mode="reg_only";
defparam sum_1_.packed_mode="false";
defparam sum_1_.lut_mask="aaaa";
assign sum_1 = sum[1];
assign sum_0 = sum[0];
endmodule /* cnter */

module shifter (
  result_3_0,
  result_3_1,
  result_3_2,
  result_3_3,
  result_3_4,
  result_3_5,
  result_3_6,
  result_3_7,
  shift_0,
  shift_1,
  a0_b_0_and2_0,
  result_0_and2_0_and2_15,
  result_0_and2_0_and2_14,
  result_0_and2_0_and2_13,
  result_0_and2_0_and2_12,
  result_0_and2_0_and2_3,
  result_0_and2_0_and2_2,
  result_0_and2_0_and2_1,
  result_0_and2_0_and2_0,
  madd_2_add5,
  madd_2_add4,
  madd_2_add3,
  madd_2_add2,
  madd_2_add1,
  madd_2_add0,
  madd_0_add0
);
output result_3_0;
output result_3_1;
output result_3_2;
output result_3_3;
output result_3_4;
output result_3_5;
output result_3_6;
output result_3_7;
input shift_0;
input shift_1;
input a0_b_0_and2_0;
output result_0_and2_0_and2_15;
output result_0_and2_0_and2_14;
output result_0_and2_0_and2_13;
output result_0_and2_0_and2_12;
output result_0_and2_0_and2_3;
output result_0_and2_0_and2_2;
output result_0_and2_0_and2_1;
output result_0_and2_0_and2_0;
input madd_2_add5;
input madd_2_add4;
input madd_2_add3;
input madd_2_add2;
input madd_2_add1;
input madd_2_add0;
input madd_0_add0;
wire result_3_0 ;
wire result_3_1 ;
wire result_3_2 ;
wire result_3_3 ;
wire result_3_4 ;
wire result_3_5 ;
wire result_3_6 ;
wire result_3_7 ;
wire shift_0 ;
wire shift_1 ;
wire a0_b_0_and2_0 ;
wire result_0_and2_0_and2_15 ;
wire result_0_and2_0_and2_14 ;
wire result_0_and2_0_and2_13 ;
wire result_0_and2_0_and2_12 ;
wire result_0_and2_0_and2_3 ;
wire result_0_and2_0_and2_2 ;
wire result_0_and2_0_and2_1 ;
wire result_0_and2_0_and2_0 ;
wire madd_2_add5 ;
wire madd_2_add4 ;
wire madd_2_add3 ;
wire madd_2_add2 ;
wire madd_2_add1 ;
wire madd_2_add0 ;
wire madd_0_add0 ;
wire [15:0] result_0_and2_0_and2;
wire [11:4] result_3;
wire [1:0] shift;
wire [0:0] a0_b_0_and2;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @7:14
  apex20k_lcell result_0_and2_0_and2_0_ (
	.combout(result_0_and2_0_and2[0]),
	.dataa(a0_b_0_and2[0]),
	.datab(shift[1]),
	.datac(shift[0])
);
defparam result_0_and2_0_and2_0_.operation_mode="normal";
defparam result_0_and2_0_and2_0_.output_mode="comb_only";
defparam result_0_and2_0_and2_0_.packed_mode="false";
defparam result_0_and2_0_and2_0_.lut_mask="8282";
// @7:14
  apex20k_lcell result_0_and2_0_and2_1_ (
	.combout(result_0_and2_0_and2[1]),
	.dataa(madd_0_add0),
	.datab(shift[1]),
	.datac(shift[0])
);
defparam result_0_and2_0_and2_1_.operation_mode="normal";
defparam result_0_and2_0_and2_1_.output_mode="comb_only";
defparam result_0_and2_0_and2_1_.packed_mode="false";
defparam result_0_and2_0_and2_1_.lut_mask="8282";
// @7:14
  apex20k_lcell result_0_and2_0_and2_2_ (
	.combout(result_0_and2_0_and2[2]),
	.dataa(madd_2_add0),
	.datab(shift[1]),
	.datac(shift[0])
);
defparam result_0_and2_0_and2_2_.operation_mode="normal";