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📄 cntrle.tdf

📁 Altare公司训练新人的练习题下载.rar FPGA/CPLD
💻 TDF
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SUBDESIGN cntrle 
( clk, rst, start : input;
  count[1..0] : input;
  in_sel[1..0], shift[1..0] : output;
  state_out[2..0] : output;
  done, clken, regclr : output;
)
VARIABLE 
   code : machine with states( idle,lsb,mid,msb,err);
BEGIN
	code.clk = clk;
	code.reset = rst;
CASE code is
WHEN idle =>
			IF start then
			   code = lsb;
			   in_sel[] = b"XX";
			   shift[] = b"XX";
			   done = gnd;
			   clken = vcc;
			   regclr = gnd;
			ELSE
			   code = idle;
			   in_sel[] = b"XX";
			   shift[] = b"XX";
			   done = gnd;
			   clken = vcc;
			   regclr = vcc;
			END IF;
WHEN lsb =>
			IF (!start and count[] == 0 )  then
			   code = mid;
			   in_sel[] = 0;
			   shift[] = 0;
			   done = gnd;
			   clken = gnd;
			   regclr = vcc;
			ELSE
			   code = err;
			   in_sel[] = b"XX";
			   shift[] = b"XX";
			   done = gnd;
			   clken = vcc;
			   regclr = vcc;
			END IF;
WHEN mid =>
			IF (!start and count[] == 2) then
			   code = msb;
			   in_sel[] = 2;
			   shift[] = 1;
			   done = gnd;
			   clken = gnd;
			   regclr = vcc;
			ELSIF (!start and count[] == 1) THEN
			   code = mid;
			   in_sel[] = 1;
			   shift[] = 1;
			   done = gnd;
			   clken = gnd;
			   regclr = vcc;
			ELSE
			   code = err;
			   in_sel[] = b"XX";
			   shift[] = b"XX";
			   done = gnd;
			   clken = vcc;
			   regclr = vcc;
			END IF;
WHEN msb =>
			IF (!start and count[] == 3) then
			   code = idle;
			   in_sel[] = 3;
			   shift[] = 2;
			   done = vcc;
			   clken = gnd;
			   regclr = vcc;
			ELSE
			   code = idle;
			   in_sel[] = b"XX";
			   shift[] = b"XX";
			   done = gnd;
			   clken = vcc;
			   regclr = vcc;
			END IF;
WHEN err =>
			IF start then
			   code = lsb;
			   in_sel[] = b"XX";
			   shift[] = b"XX";
			   done = gnd;
			   clken = vcc;
			   regclr = gnd;
			ELSE
			   code = err;
			   in_sel[] = b"XX";
			   shift[] = b"XX";
			   done = gnd;
			   clken = vcc;
			   regclr = vcc;
			END IF;

END CASE;
% Used by seven seg display%
CASE code is
WHEN idle =>
    state_out[] = 0;
WHEN lsb => 
	state_out[] = 1;
WHEN mid =>
	state_out[] = 2;
WHEN msb =>
	state_out[] = 3;
WHEN err =>
	state_out[] = 4; 
END CASE;
END;

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