lab2.xrf

Altare公司训练新人的练习题下载.rar FPGA/CPLD

vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, d:\cjok2\dont touch\adder.v, synplify
source_file = 2, d:\cjok2\dont touch\seven.v, synplify
source_file = 3, d:\cjok2\dont touch\regis16.v, synplify
source_file = 4, d:\cjok2\dont touch\multshrc.v, synplify
source_file = 5, d:\cjok2\dont touch\cntrle.v, synplify
source_file = 6, d:\cjok2\dont touch\cnter.v, synplify
source_file = 7, d:\cjok2\dont touch\shifter.v, synplify
source_file = 8, d:\cjok2\dont touch\lab2.v, synplify
design_name=lab2
instance = port, result[15:0], , lab2, 8, 9:14:9:19
instance = port, sega, , lab2, 8, 7:7:7:10
instance = port, segb, , lab2, 8, 7:13:7:16
instance = port, segc, , lab2, 8, 7:19:7:22
instance = port, segd, , lab2, 8, 7:25:7:28
instance = port, sege, , lab2, 8, 7:31:7:34
instance = port, segf, , lab2, 8, 8:3:8:6
instance = port, segg, , lab2, 8, 8:9:8:12
instance = port, done_flag, , lab2, 8, 8:15:8:23
instance = port, start, , lab2, 8, 6:6:6:10
instance = port, reset, , lab2, 8, 6:13:6:17
instance = port, clk, , lab2, 8, 6:20:6:22
instance = port, dataa[7:0], , lab2, 8, 5:12:5:16
instance = port, datab[7:0], , lab2, 8, 5:19:5:23
instance = comp, datab_in_7_, , lab2, 8, 5:19:5:23
instance = comp, datab_in_6_, , lab2, 8, 5:19:5:23
instance = comp, datab_in_5_, , lab2, 8, 5:19:5:23
instance = comp, datab_in_4_, , lab2, 8, 5:19:5:23
instance = comp, datab_in_3_, , lab2, 8, 5:19:5:23
instance = comp, datab_in_2_, , lab2, 8, 5:19:5:23
instance = comp, datab_in_1_, , lab2, 8, 5:19:5:23
instance = comp, datab_in_0_, , lab2, 8, 5:19:5:23
instance = comp, dataa_in_7_, , lab2, 8, 5:12:5:16
instance = comp, dataa_in_6_, , lab2, 8, 5:12:5:16
instance = comp, dataa_in_5_, , lab2, 8, 5:12:5:16
instance = comp, dataa_in_4_, , lab2, 8, 5:12:5:16
instance = comp, dataa_in_3_, , lab2, 8, 5:12:5:16
instance = comp, dataa_in_2_, , lab2, 8, 5:12:5:16
instance = comp, dataa_in_1_, , lab2, 8, 5:12:5:16
instance = comp, dataa_in_0_, , lab2, 8, 5:12:5:16
instance = comp, clk_in, , lab2, 8, 6:20:6:22
instance = comp, reset_in, , lab2, 8, 6:13:6:17
instance = comp, start_in, , lab2, 8, 6:6:6:10
instance = comp, done_flag_out_Z, , lab2, 8, 8:15:8:23
instance = comp, segg_out_Z, , lab2, 8, 8:9:8:12
instance = comp, segf_out_Z, , lab2, 8, 8:3:8:6
instance = comp, sege_out_Z, , lab2, 8, 7:31:7:34
instance = comp, segd_out, , lab2, 8, 7:25:7:28
instance = comp, segc_out_Z, , lab2, 8, 7:19:7:22
instance = comp, segb_out_Z, , lab2, 8, 7:13:7:16
instance = comp, sega_out, , lab2, 8, 7:7:7:10
instance = comp, result_out_15_, , lab2, 8, 9:14:9:19
instance = comp, result_out_14_, , lab2, 8, 9:14:9:19
instance = comp, result_out_13_, , lab2, 8, 9:14:9:19
instance = comp, result_out_12_, , lab2, 8, 9:14:9:19
instance = comp, result_out_11_, , lab2, 8, 9:14:9:19
instance = comp, result_out_10_, , lab2, 8, 9:14:9:19
instance = comp, result_out_9_, , lab2, 8, 9:14:9:19
instance = comp, result_out_8_, , lab2, 8, 9:14:9:19
instance = comp, result_out_7_, , lab2, 8, 9:14:9:19
instance = comp, result_out_6_, , lab2, 8, 9:14:9:19
instance = comp, result_out_5_, , lab2, 8, 9:14:9:19
instance = comp, result_out_4_, , lab2, 8, 9:14:9:19
instance = comp, result_out_3_, , lab2, 8, 9:14:9:19
instance = comp, result_out_2_, , lab2, 8, 9:14:9:19
instance = comp, result_out_1_, , lab2, 8, 9:14:9:19
instance = comp, result_out_0_, , lab2, 8, 9:14:9:19
instance = comp, u7, , lab2, 8, 35:6:35:7
instance = comp, u6, , lab2, 8, 33:6:33:7
instance = comp, u5, , lab2, 8, 30:8:30:9
instance = comp, u3, , lab2, 8, 24:6:24:7
instance = comp, u2, , lab2, 8, 22:8:22:9
instance = comp, u1, , lab2, 8, 20:9:20:10
instance = comp, u4, , lab2, 8, 26:7:26:8
instance = comp, u2_false, , lab2, 1, 1:1:1:2
instance = comp, u2_true, , lab2, 1, 1:1:1:2
instance = comp, G_67_Z, , lab2, 6, 11:12:11:18
design_name=multshrc
instance = comp, u2_false, , multshrc, 1, 1:1:1:2
instance = comp, y_madd_0_add0, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_0_add1, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_0_add2, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_0_add3, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_1_add1, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_1_add2, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_1_add3, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_1_add4, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_2_add0, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_2_add1, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_2_add2, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_2_add3, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_2_add4, , multshrc, 4, 35:6:35:18
instance = comp, y_madd_2_add5, , multshrc, 4, 35:6:35:18
instance = comp, y_a0_b_0_and2_0_, , multshrc, 4, 35:6:35:18
instance = comp, int_a_0_, , multshrc, 4, 15:2:15:5
instance = comp, y_a0_b_0_and2_1_, , multshrc, 4, 35:6:35:18
instance = comp, y_a0_b_0_and2_2_, , multshrc, 4, 35:6:35:18
instance = comp, y_a0_b_0_and2_3_, , multshrc, 4, 35:6:35:18
instance = comp, int_b_3_, , multshrc, 4, 15:2:15:5
instance = comp, y_a1_b_0_and2_0_, , multshrc, 4, 35:6:35:18
instance = comp, int_a_1_, , multshrc, 4, 15:2:15:5
instance = comp, y_a1_b_0_and2_1_, , multshrc, 4, 35:6:35:18
instance = comp, y_a1_b_0_and2_2_, , multshrc, 4, 35:6:35:18
instance = comp, y_a2_b_0_and2_0_, , multshrc, 4, 35:6:35:18
instance = comp, int_a_2_, , multshrc, 4, 15:2:15:5
instance = comp, y_a2_b_0_and2_1_, , multshrc, 4, 35:6:35:18
instance = comp, y_a2_b_0_and2_2_, , multshrc, 4, 35:6:35:18
instance = comp, y_a2_b_0_and2_3_, , multshrc, 4, 35:6:35:18
instance = comp, y_a3_b_0_and2_0_, , multshrc, 4, 35:6:35:18
instance = comp, int_a_3_, , multshrc, 4, 15:2:15:5
instance = comp, y_a3_b_0_and2_1_, , multshrc, 4, 35:6:35:18
instance = comp, y_a3_b_0_and2_2_, , multshrc, 4, 35:6:35:18
design_name=shifter
instance = comp, u2_false, , shifter, 1, 1:1:1:2
instance = comp, result_0_and2_0_and2_0_, , shifter, 7, 14:6:18:18
instance = comp, result_0_and2_0_and2_1_, , shifter, 7, 14:6:18:18
instance = comp, result_0_and2_0_and2_2_, , shifter, 7, 14:6:18:18
instance = comp, result_0_and2_0_and2_3_, , shifter, 7, 14:6:18:18
instance = comp, result_0_and2_0_and2_12_, , shifter, 7, 14:6:18:18
instance = comp, result_0_and2_0_and2_13_, , shifter, 7, 14:6:18:18
instance = comp, result_0_and2_0_and2_14_, , shifter, 7, 14:6:18:18
instance = comp, result_0_and2_0_and2_15_, , shifter, 7, 14:6:18:18
instance = comp, result_3_11_, , shifter, 7, 14:2:14:3
instance = comp, result_3_10_, , shifter, 7, 14:2:14:3
instance = comp, result_3_9_, , shifter, 7, 14:2:14:3
instance = comp, result_3_8_, , shifter, 7, 14:2:14:3
instance = comp, result_3_7_, , shifter, 7, 14:2:14:3
instance = comp, result_3_6_, , shifter, 7, 14:2:14:3
instance = comp, result_3_5_, , shifter, 7, 14:2:14:3
instance = comp, result_3_4_, , shifter, 7, 14:2:14:3
design_name=cnter
instance = comp, u2_false, , cnter, 1, 1:1:1:2
instance = comp, sum_0_, , cnter, 6, 8:0:8:5
instance = comp, sum_1_, , cnter, 6, 8:0:8:5
design_name=regis16
instance = comp, u2_false, , regis16, 1, 1:1:1:2
instance = comp, out_reg_0_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_1_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_2_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_3_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_4_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_5_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_6_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_7_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_8_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_9_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_10_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_11_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_12_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_13_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_14_, , regis16, 3, 9:0:9:5
instance = comp, out_reg_15_, , regis16, 3, 9:0:9:5
design_name=adder
instance = comp, u2_false, , adder, 1, 1:1:1:2
instance = comp, sum_1_add0_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add1_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add2_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add3_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add4_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add5_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add6_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add7_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add8_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add9_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add10_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add11_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add12_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add13_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add14_0, , adder, 1, 6:18:6:22
instance = comp, sum_1_add15_0, , adder, 1, 6:18:6:22
design_name=seven
instance = comp, u2_false, , seven, 1, 1:1:1:2
instance = comp, f_0_0, , seven, 2, 10:2:10:5
instance = comp, c_i_i, , seven, 2, 10:2:10:5
instance = comp, g_i_and2_0_and2, , seven, 2, 10:2:10:5
instance = comp, e_i_and2_i_or2, , seven, 2, 10:2:10:5
instance = comp, un1_inp_5_0_and2, , seven, 2, 20:3:20:8