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#LIBRARY="#terminals"
#REFERENCE="Clk1024Hz"
#SYMBOL="Output"
#VERILOG_TYPE="wire"
}
COORD (1750,130)
VERTEXES ( (2,1059) )
}
TEXT 493, 0, 0
{
TEXT "$#REFERENCE"
RECT (1802,113,1945,148)
ALIGN 4
MARGINS (1,1)
PARENT 492
}
INSTANCE 497, 0, 0
{
VARIABLES
{
#COMPONENT="Output"
#LIBRARY="#terminals"
#REFERENCE="Clk512Hz"
#SYMBOL="Output"
#VERILOG_TYPE="wire"
}
COORD (1750,160)
VERTEXES ( (2,1062) )
}
TEXT 498, 0, 0
{
TEXT "$#REFERENCE"
RECT (1802,143,1929,178)
ALIGN 4
MARGINS (1,1)
PARENT 497
}
INSTANCE 502, 0, 0
{
VARIABLES
{
#COMPONENT="Output"
#LIBRARY="#terminals"
#REFERENCE="Clk2Hz"
#SYMBOL="Output"
#VERILOG_TYPE="wire"
}
COORD (1750,250)
VERTEXES ( (2,1071) )
}
TEXT 503, 0, 0
{
TEXT "$#REFERENCE"
RECT (1802,233,1897,268)
ALIGN 4
MARGINS (1,1)
PARENT 502
}
NET WIRE 534, 0, 0
NET WIRE 538, 0, 0
NET WIRE 542, 0, 0
NET WIRE 546, 0, 0
NET WIRE 550, 0, 0
NET WIRE 554, 0, 0
CONTINUOUSASSIGN 584, 0, 0
{
LABEL "ContinuousAssignments_1"
TEXT
"assign Clk1024Hz\t=Count[1];\n"+
"assign Clk512Hz \t=Count[2];\n"+
"assign Clk8Hz\t\t\t=Count[8];\n"+
"assign Clk4Hz\t\t\t=Count[9];\n"+
"assign Clk2Hz\t\t\t=Count[10];\n"+
"assign Clk1Hz\t\t\t=Count[11];\n"+
"assign Clk8HzTC =&Count[8:0];"
RECT (910,90,1590,370)
MARGINS (20,20)
MULTILINE
SYNTAXCOLORED
SHOWLABEL
SHOWTEXT
CORNER 10
VTX ( 1053, 1060, 1063, 1066, 1069, 1072, 1075, 1078 )
}
VTX 787, 0, 0
{
COORD (470,490)
}
VTX 793, 0, 0
{
COORD (470,530)
}
WIRE 794, 0, 0
{
NET 242
VTX 256, 787
}
VTX 802, 0, 0
{
COORD (420,530)
}
WIRE 803, 0, 0
{
NET 192
VTX 187, 802
}
WIRE 804, 0, 0
{
NET 192
VTX 802, 793
}
VTX 805, 0, 0
{
COORD (610,570)
}
VTX 806, 0, 0
{
COORD (610,710)
}
WIRE 808, 0, 0
{
NET 59
VTX 806, 805
}
WIRE 809, 0, 0
{
NET 59
VTX 313, 806
}
VTX 841, 0, 0
{
COORD (980,590)
}
VTX 842, 0, 0
{
COORD (1080,670)
}
VTX 845, 0, 0
{
COORD (980,630)
}
VTX 846, 0, 0
{
COORD (430,370)
}
WIRE 847, 0, 0
{
NET 242
VTX 256, 846
}
VTX 848, 0, 0
{
COORD (970,370)
}
WIRE 849, 0, 0
{
NET 242
VTX 846, 848
}
VTX 850, 0, 0
{
COORD (970,590)
}
WIRE 851, 0, 0
{
NET 242
VTX 848, 850
}
WIRE 852, 0, 0
{
NET 242
VTX 850, 841
}
VTX 853, 0, 0
{
COORD (1080,710)
}
WIRE 854, 0, 0
{
NET 59
VTX 806, 853
}
WIRE 855, 0, 0
{
NET 59
VTX 853, 842
}
WIRE 857, 0, 0
{
NET 192
VTX 187, 845
}
INSTANCE 914, 0, 0
{
VARIABLES
{
#COMPONENT="Output"
#LIBRARY="#terminals"
#REFERENCE="Clk8HzTC"
#SYMBOL="Output"
#VERILOG_TYPE="wire"
}
COORD (1750,310)
VERTEXES ( (2,1077) )
}
TEXT 915, 0, 0
{
TEXT "$#REFERENCE"
RECT (1802,293,1937,328)
ALIGN 4
MARGINS (1,1)
PARENT 914
}
NET WIRE 921, 0, 0
NET WIRE 923, 0, 0
{
VARIABLES
{
#NAME="Clk1HzTC"
#VERILOG_TYPE="wire"
}
}
VTX 1001, 0, 0
{
COORD (1180,630)
}
VTX 1002, 0, 0
{
COORD (1780,630)
}
VTX 1003, 0, 0
{
COORD (750,530)
}
VTX 1004, 0, 0
{
COORD (1780,530)
}
WIRE 1005, 0, 0
{
NET 164
VTX 1001, 1002
VARIABLES
{
#NAMED="1"
}
}
WIRE 1006, 0, 0
{
NET 923
VTX 1003, 1004
VARIABLES
{
#NAMED="1"
}
}
VTX 1052, 0, 0
{
COORD (750,490)
}
VTX 1053, 0, 0
{
COORD (910,220)
}
VTX 1054, 0, 0
{
COORD (900,490)
}
BUS 1055, 0, 0
{
NET 358
VTX 1052, 1054
VARIABLES
{
#NAMED="1"
}
}
VTX 1056, 0, 0
{
COORD (900,220)
}
BUS 1057, 0, 0
{
NET 358
VTX 1054, 1056
}
BUS 1058, 0, 0
{
NET 358
VTX 1056, 1053
}
VTX 1059, 0, 0
{
COORD (1750,130)
}
VTX 1060, 0, 0
{
COORD (1590,130)
}
WIRE 1061, 0, 0
{
NET 534
VTX 1059, 1060
}
VTX 1062, 0, 0
{
COORD (1750,160)
}
VTX 1063, 0, 0
{
COORD (1590,160)
}
WIRE 1064, 0, 0
{
NET 538
VTX 1062, 1063
}
VTX 1065, 0, 0
{
COORD (1750,190)
}
VTX 1066, 0, 0
{
COORD (1590,190)
}
WIRE 1067, 0, 0
{
NET 542
VTX 1065, 1066
}
VTX 1068, 0, 0
{
COORD (1750,220)
}
VTX 1069, 0, 0
{
COORD (1590,220)
}
WIRE 1070, 0, 0
{
NET 546
VTX 1068, 1069
}
VTX 1071, 0, 0
{
COORD (1750,250)
}
VTX 1072, 0, 0
{
COORD (1590,250)
}
WIRE 1073, 0, 0
{
NET 550
VTX 1071, 1072
}
VTX 1074, 0, 0
{
COORD (1750,280)
}
VTX 1075, 0, 0
{
COORD (1590,280)
}
WIRE 1076, 0, 0
{
NET 554
VTX 1074, 1075
}
VTX 1077, 0, 0
{
COORD (1750,310)
}
VTX 1078, 0, 0
{
COORD (1590,310)
}
WIRE 1079, 0, 0
{
NET 921
VTX 1077, 1078
}
}
}
PAGE ""
{
PAGEHEADER
{
PAGESIZE (2200,1700)
MARGINS (200,200,200,200)
RECT (0,0,0,0)
VARIABLES
{
#BLOCKTABLE_PAGE="1"
#BLOCKTABLE_TEMPL="1"
#BLOCKTABLE_VISIBLE="0"
#MODIFIED="1004440810"
}
}
BODY
{
TEXT 1129, 0, 0
{
PAGEALIGN 10
OUTLINE 5,1, (0,0,0)
TEXT "Created:"
RECT (1140,1386,1257,1439)
ALIGN 4
MARGINS (1,10)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
}
TEXT 1130, 0, 0
{
PAGEALIGN 10
TEXT "$CREATIONDATE"
RECT (1310,1380,1980,1440)
ALIGN 4
MARGINS (1,1)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
UPDATE 0
}
TEXT 1131, 0, 0
{
PAGEALIGN 10
TEXT "Title:"
RECT (1141,1444,1212,1497)
ALIGN 4
MARGINS (1,10)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
}
TEXT 1132, 0, 0
{
PAGEALIGN 10
OUTLINE 5,1, (0,0,0)
TEXT "$TITLE"
RECT (1310,1440,1980,1500)
ALIGN 4
MARGINS (1,1)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
UPDATE 0
}
LINE 1133, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (1130,1380), (2000,1380) )
FILL (1,(0,0,0),0)
}
LINE 1134, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (1130,1440), (2000,1440) )
FILL (1,(0,0,0),0)
}
LINE 1135, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (1300,1380), (1300,1500) )
}
LINE 1136, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (2000,1500), (2000,1240), (1130,1240), (1130,1500), (2000,1500) )
FILL (1,(0,0,0),0)
}
TEXT 1137, 0, 0
{
PAGEALIGN 10
TEXT
"(C)ALDEC. Inc\n"+
"2230 Corporate Circle\n"+
"Henderson, NV 89074"
RECT (1140,1260,1435,1361)
MARGINS (1,1)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
MULTILINE
}
LINE 1138, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (1440,1240), (1440,1380) )
}
LINE 1139, 0, 0
{
PAGEALIGN 10
OUTLINE 0,4, (0,4,255)
POINTS ( (1616,1304), (1682,1304) )
FILL (0,(0,4,255),0)
}
LINE 1140, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1585,1300), (1585,1300) )
FILL (0,(0,4,255),0)
}
LINE 1141, 0, 0
{
PAGEALIGN 10
OUTLINE 0,3, (0,4,255)
POINTS ( (1634,1304), (1650,1264) )
FILL (0,(0,4,255),0)
}
TEXT 1142, -4, 0
{
PAGEALIGN 10
OUTLINE 5,0, (49,101,255)
TEXT "ALDEC"
RECT (1663,1246,1961,1348)
MARGINS (1,1)
COLOR (0,4,255)
FONT (36,0,0,700,0,1,0,"Arial")
}
LINE 1143, 0, 0
{
PAGEALIGN 10
OUTLINE 0,3, (0,4,255)
POINTS ( (1576,1264), (1551,1327) )
FILL (0,(0,4,255),0)
}
BEZIER 1144, 0, 0
{
PAGEALIGN 10
OUTLINE 0,3, (0,4,255)
FILL (0,(0,4,255),0)
ORIGINS ( (1583,1290), (1616,1304), (1583,1315), (1583,1290) )
CONTROLS (( (1607,1290), (1615,1289)),( (1613,1315), (1610,1315)),( (1583,1307), (1583,1302)) )
}
LINE 1145, 0, 0
{
PAGEALIGN 10
OUTLINE 0,4, (0,4,255)
POINTS ( (1495,1311), (1583,1311) )
FILL (0,(0,4,255),0)
}
LINE 1146, 0, 0
{
PAGEALIGN 10
OUTLINE 0,4, (0,4,255)
POINTS ( (1502,1294), (1583,1294) )
FILL (0,(0,4,255),0)
}
LINE 1147, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1688,1271), (1511,1271) )
FILL (0,(0,4,255),0)
}
LINE 1148, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1686,1278), (1508,1278) )
FILL (0,(0,4,255),0)
}
LINE 1149, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1700,1286), (1506,1286) )
FILL (0,(0,4,255),0)
}
LINE 1150, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1702,1294), (1510,1294) )
FILL (0,(0,4,255),0)
}
LINE 1151, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1615,1302), (1499,1302) )
FILL (0,(0,4,255),0)
}
LINE 1152, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1680,1311), (1495,1311) )
FILL (0,(0,4,255),0)
}
LINE 1153, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1673,1319), (1492,1319) )
FILL (0,(0,4,255),0)
}
TEXT 1154, 0, 0
{
PAGEALIGN 10
TEXT "The Design Verification Company"
RECT (1482,1336,1934,1370)
MARGINS (1,1)
COLOR (0,4,255)
FONT (12,0,0,700,1,1,0,"Arial")
}
LINE 1155, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1667,1327), (1489,1327) )
FILL (0,(0,4,255),0)
}
LINE 1156, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1690,1264), (1514,1264) )
FILL (0,(0,4,255),0)
}
}
}
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