frequencedivde.bde

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SCHM0102

HEADER
{
 FREEID 1157
 VARIABLES
 {
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #LANGUAGE="VERILOG"
  #MODULE="FrequenceDivde"
  AUTHOR="zjj"
  COMPANY="hust"
  CREATIONDATE="2003-03-14"
  TITLE="No Title"
 }
 SYMBOL "#default" "CountTC" "CountTC"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #GENERIC0="Size:integer:=3"
    #GENERIC1="Begin:integer:=0"
    #GENERIC2="End:integer:=7"
    #LANGUAGE="VERILOG"
    #MODIFIED="1047647930"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,280,100)
    FREEID 12
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,260,80)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,50,54,74)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (121,10,255,34)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (126,46,155,70)
     ALIGN 6
     MARGINS (1,1)
     PARENT 6
     ORIENTATION 4
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (227,50,255,74)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,10,78,34)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    PIN  2, 0, 0
    {
     COORD (0,60)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="CE"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (280,20)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="Count(Size-1:0)"
      #NUMBER="0"
      #SIDE="right"
      #VERILOG_TYPE="reg"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (140,100)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="Clk"
      #NUMBER="0"
      #SIDE="bottom"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (0,-20) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (280,60)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="TC"
      #NUMBER="0"
      #SIDE="right"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,20)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="Reset"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "DivideTC" "DivideTC"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #GENERIC0="Size:integer:=3"
    #GENERIC1="Begin:integer:=0"
    #GENERIC2="End:integer:=7"
    #LANGUAGE="VERILOG"
    #MODIFIED="1047648014"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,200,100)
    FREEID 10
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,180,80)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,50,54,74)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (147,50,175,74)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (91,48,120,72)
     ALIGN 6
     MARGINS (1,1)
     PARENT 6
     ORIENTATION 4
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,10,78,34)
     ALIGN 4
     MARGINS (1,1)
     PARENT 8
    }
    PIN  2, 0, 0
    {
     COORD (0,60)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="CE"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (200,60)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="TC"
      #NUMBER="0"
      #SIDE="right"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (100,100)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="Clk"
      #NUMBER="0"
      #SIDE="bottom"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (0,-20) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (0,20)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="Reset"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
}

PAGE ""
{
 PAGEHEADER
 {
  PAGESIZE (2200,1700)
  MARGINS (200,200,200,200)
  RECT (0,0,100,200)
 }
 
 BODY
 {
  INSTANCE  29, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="CountTC"
    #GENERIC0="Begin : integer := 0"
    #GENERIC1="End : integer := 4095"
    #GENERIC2="Size : integer := 12"
    #LIBRARY="#default"
    #REFERENCE="U_Divide4096"
    #SYMBOL="CountTC"
   }
   COORD (470,470)
   VERTEXES ( (10,787), (2,793), (6,805), (8,1003), (4,1052) )
  }
  TEXT  30, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (470,434,653,469)
   ALIGN 8
   MARGINS (1,1)
   PARENT 29
  }
  TEXT  34, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (470,570,589,605)
   MARGINS (1,1)
   PARENT 29
  }
  INSTANCE  38, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="Clk4096Hz"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (320,710)
   VERTEXES ( (2,313) )
  }
  TEXT  39, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (126,693,269,728)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  NET WIRE  59, 0, 0
  INSTANCE  60, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="DivideTC"
    #GENERIC0="Begin : integer := 23"
    #GENERIC1="End : integer := 63"
    #GENERIC2="Size : integer := 6"
    #LIBRARY="#default"
    #REFERENCE="U_Divide41"
    #SYMBOL="DivideTC"
   }
   COORD (980,570)
   VERTEXES ( (8,841), (2,845), (6,842), (4,1001) )
  }
  TEXT  61, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (980,534,1131,569)
   ALIGN 8
   MARGINS (1,1)
   PARENT 60
  }
  TEXT  62, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (980,670,1102,705)
   MARGINS (1,1)
   PARENT 60
  }
  NET WIRE  164, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk100HzCE"
   }
  }
  TEXT  165, 0, 0
  {
   TEXT "$#NAME"
   RECT (1248,601,1386,630)
   ALIGN 9
   MARGINS (1,1)
   PARENT 1005
  }
  VTX  186, 0, 0
  {
   COORD (360,630)
  }
  VTX  187, 0, 0
  {
   COORD (420,630)
  }
  WIRE  188, 0, 0
  {
   NET 192
   VTX 186, 187
  }
  NET WIRE  192, 0, 0
  INSTANCE  193, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Power"
    #LIBRARY="#connectors"
    #REFERENCE="VCC"
    #SYMBOL="Power"
   }
   COORD (360,630)
   ORIENTATION 2
   VERTEXES ( (2,186) )
  }
  TEXT  194, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (286,583,349,618)
   ALIGN 6
   MARGINS (1,1)
   PARENT 193
  }
  NET WIRE  242, 0, 0
  VTX  256, 0, 0
  {
   COORD (430,490)
  }
  INSTANCE  270, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="Reset"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (300,490)
   VERTEXES ( (2,391) )
  }
  TEXT  271, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (171,473,249,508)
   ALIGN 6
   MARGINS (1,1)
   PARENT 270
  }
  VTX  313, 0, 0
  {
   COORD (320,710)
  }
  TEXT  354, 0, 0
  {
   TEXT "$#NAME"
   RECT (784,500,894,529)
   ALIGN 9
   MARGINS (1,1)
   PARENT 1006
  }
  NET BUS  358, 0, 0
  {
   VARIABLES
   {
    #NAME="Count(11:0)"
    #VERILOG_TYPE="wire"
   }
  }
  TEXT  359, 0, 0
  {
   TEXT "$#NAME"
   RECT (746,451,875,480)
   ALIGN 9
   MARGINS (1,1)
   PARENT 1055
  }
  VTX  391, 0, 0
  {
   COORD (300,490)
  }
  WIRE  392, 0, 0
  {
   NET 242
   VTX 256, 391
  }
  INSTANCE  393, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #LIBRARY="#terminals"
    #REFERENCE="Clk100HzCE"
    #SYMBOL="Output"
   }
   COORD (1780,630)
   VERTEXES ( (2,1002) )
  }
  TEXT  394, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1832,613,1999,648)
   ALIGN 4
   MARGINS (1,1)
   PARENT 393
  }
  INSTANCE  398, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #LIBRARY="#terminals"
    #REFERENCE="Clk1Hz"
    #SYMBOL="Output"
    #VERILOG_TYPE="wire"
   }
   COORD (1750,280)
   VERTEXES ( (2,1074) )
  }
  TEXT  399, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1802,263,1897,298)
   ALIGN 4
   MARGINS (1,1)
   PARENT 398
  }
  INSTANCE  403, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #LIBRARY="#terminals"
    #REFERENCE="Clk8Hz"
    #SYMBOL="Output"
    #VERILOG_TYPE="wire"
   }
   COORD (1750,190)
   VERTEXES ( (2,1065) )
  }
  TEXT  404, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1802,173,1897,208)
   ALIGN 4
   MARGINS (1,1)
   PARENT 403
  }
  INSTANCE  485, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #LIBRARY="#terminals"
    #REFERENCE="Clk4Hz"
    #SYMBOL="Output"
    #VERILOG_TYPE="wire"
   }
   COORD (1750,220)
   VERTEXES ( (2,1068) )
  }
  TEXT  486, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1802,203,1897,238)
   ALIGN 4
   MARGINS (1,1)
   PARENT 485
  }
  INSTANCE  487, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #LIBRARY="#terminals"
    #REFERENCE="Clk1HzTC"
    #SYMBOL="Output"
    #VERILOG_TYPE="wire"
   }
   COORD (1780,530)
   VERTEXES ( (2,1004) )
  }
  TEXT  488, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1832,513,1967,548)
   ALIGN 4
   MARGINS (1,1)
   PARENT 487
  }
  INSTANCE  492, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"