keyinput.v

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`timescale 1ns / 100ps
module KeyInput(KeyIn,Clk,CE,Reset,KeyOut,KeyCP);
	input KeyIn,Clk,CE,Reset;
	output KeyOut,KeyCP;
	reg Q1,Q2,Q3;
	wire BothH,BothL;
	
	always @(negedge Reset or posedge Clk)	  //two delay 
		if (!Reset)	begin Q1<=0; Q2<=0; Q3<=0; end
		else if(CE)
			begin Q1<=KeyIn; Q2<=Q1; Q3<=KeyOut; end
		
	assign BothH=Q1 & Q2;
	assign BothL=~Q1&~Q2;
	SRLatch U_SRLatch(BothH,BothL,KeyOut,);
	assign KeyCP=KeyOut & ~Q3;
	
endmodule