count60.bak

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SCHM0102

HEADER
{
 FREEID 197
 VARIABLES
 {
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #LANGUAGE="VERILOG"
  #MODULE="Count60"
  AUTHOR="zjj"
  COMPANY="hust"
  CREATIONDATE="2003-03-14"
  TITLE="No Title"
 }
 SYMBOL "#default" "CountRange" "CountRange"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #GENERIC0="Size:integer:=3"
    #GENERIC1="Begin:integer:=0"
    #GENERIC2="End:integer:=7"
    #LANGUAGE="VERILOG"
    #MODIFIED="1047638920"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,240,100)
    FREEID 12
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,220,80)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,50,54,74)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (81,10,215,34)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (111,48,140,72)
     ALIGN 6
     MARGINS (1,1)
     PARENT 6
     ORIENTATION 4
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (187,50,215,74)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,10,78,34)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    PIN  2, 0, 0
    {
     COORD (0,60)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="CE"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (240,20)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="Count(Size-1:0)"
      #NUMBER="0"
      #VERILOG_TYPE="reg"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (120,100)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="Clk"
      #NUMBER="0"
      #SIDE="bottom"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (0,-20) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (240,60)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="TC"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,20)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="Reset"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
}

PAGE ""
{
 PAGEHEADER
 {
  PAGESIZE (2200,1700)
  MARGINS (200,200,200,200)
  RECT (0,0,100,200)
 }
 
 BODY
 {
  INSTANCE  29, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="CountRange"
    #LIBRARY="#default"
    #REFERENCE="U1"
    #SYMBOL="CountRange"
   }
   COORD (460,440)
   VERTEXES ( (6,53), (8,64), (10,140), (2,154) )
  }
  TEXT  30, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (460,404,499,439)
   ALIGN 8
   MARGINS (1,1)
   PARENT 29
  }
  TEXT  34, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (460,541,624,576)
   MARGINS (1,1)
   PARENT 29
  }
  INSTANCE  38, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="CountRange"
    #LIBRARY="#default"
    #REFERENCE="U2"
    #SYMBOL="CountRange"
   }
   COORD (880,440)
   VERTEXES ( (2,65), (6,63), (10,74), (8,166) )
  }
  TEXT  39, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (880,404,919,439)
   ALIGN 8
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  40, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (880,541,1044,576)
   MARGINS (1,1)
   PARENT 38
  }
  VTX  53, 0, 0
  {
   COORD (580,540)
  }
  VTX  54, 0, 0
  {
   COORD (580,630)
  }
  WIRE  57, 0, 0
  {
   NET 58
   VTX 53, 54
  }
  NET WIRE  58, 0, 0
  NET WIRE  61, 0, 0
  VTX  63, 0, 0
  {
   COORD (1000,540)
  }
  VTX  64, 0, 0
  {
   COORD (700,500)
  }
  VTX  65, 0, 0
  {
   COORD (880,500)
  }
  VTX  66, 0, 0
  {
   COORD (1000,630)
  }
  WIRE  67, 0, 0
  {
   NET 58
   VTX 63, 66
  }
  WIRE  68, 0, 0
  {
   NET 58
   VTX 66, 54
  }
  WIRE  69, 0, 0
  {
   NET 61
   VTX 64, 65
  }
  NET WIRE  72, 0, 0
  VTX  74, 0, 0
  {
   COORD (880,460)
  }
  VTX  75, 0, 0
  {
   COORD (810,460)
  }
  NET WIRE  76, 0, 0
  WIRE  77, 0, 0
  {
   NET 76
   VTX 74, 75
  }
  INSTANCE  78, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #LIBRARY="#terminals"
    #REFERENCE="TC"
    #SYMBOL="Output"
    #VERILOG_TYPE="wire"
   }
   COORD (1340,500)
   VERTEXES ( (2,167) )
  }
  TEXT  79, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1392,483,1434,518)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  INSTANCE  83, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="BusOutput0(7:0)"
    #SYMBOL="BusOutput"
   }
   COORD (1380,340)
  }
  TEXT  84, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1432,323,1647,358)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  INSTANCE  88, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="Reset"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (340,460)
   VERTEXES ( (2,141) )
  }
  TEXT  89, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (211,443,289,478)
   ALIGN 6
   MARGINS (1,1)
   PARENT 88
  }
  INSTANCE  93, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="Clk"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (330,630)
   VERTEXES ( (2,143) )
  }
  TEXT  94, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (235,613,279,648)
   ALIGN 6
   MARGINS (1,1)
   PARENT 93
  }
  VTX  140, 0, 0
  {
   COORD (460,460)
  }
  VTX  141, 0, 0
  {
   COORD (340,460)
  }
  WIRE  142, 0, 0
  {
   NET 72
   VTX 140, 141
  }
  VTX  143, 0, 0
  {
   COORD (330,630)
  }
  WIRE  144, 0, 0
  {
   NET 58
   VTX 54, 143
  }
  INSTANCE  145, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="CE"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (340,500)
   VERTEXES ( (2,155) )
  }
  TEXT  146, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (247,483,289,518)
   ALIGN 6
   MARGINS (1,1)
   PARENT 145
  }
  NET WIRE  150, 0, 0
  VTX  154, 0, 0
  {
   COORD (460,500)
  }
  VTX  155, 0, 0
  {
   COORD (340,500)
  }
  WIRE  156, 0, 0
  {
   NET 150
   VTX 154, 155
  }
  NET WIRE  161, 0, 0
  {
   VARIABLES
   {
    #NAME="TC"
    #VERILOG_TYPE="wire"
   }
  }
  TEXT  162, 0, 0
  {
   TEXT "$#NAME"
   RECT (1186,470,1219,499)
   ALIGN 9
   MARGINS (1,1)
   PARENT 168
  }
  VTX  166, 0, 0
  {
   COORD (1120,500)
  }
  VTX  167, 0, 0
  {
   COORD (1340,500)
  }
  WIRE  168, 0, 0
  {
   NET 161
   VTX 166, 167
   VARIABLES
   {
    #NAMED="1"
   }
  }
 }
 
}

PAGE ""
{
 PAGEHEADER
 {
  PAGESIZE (2200,1700)
  MARGINS (200,200,200,200)
  RECT (0,0,0,0)
  VARIABLES
  {
   #BLOCKTABLE_PAGE="1"
   #BLOCKTABLE_TEMPL="1"
   #BLOCKTABLE_VISIBLE="0"
   #MODIFIED="1004440810"
  }
 }
 
 BODY
 {
  TEXT  169, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 5,1, (0,0,0)
   TEXT "Created:"
   RECT (1140,1386,1257,1439)
   ALIGN 4
   MARGINS (1,10)
   COLOR (0,0,0)
   FONT (12,0,0,700,0,0,0,"Arial")
  }
  TEXT  170, 0, 0
  {
   PAGEALIGN 10
   TEXT "$CREATIONDATE"
   RECT (1310,1380,1980,1440)
   ALIGN 4
   MARGINS (1,1)
   COLOR (0,0,0)
   FONT (12,0,0,700,0,0,0,"Arial")
   UPDATE 0
  }
  TEXT  171, 0, 0
  {
   PAGEALIGN 10
   TEXT "Title:"
   RECT (1141,1444,1212,1497)
   ALIGN 4
   MARGINS (1,10)
   COLOR (0,0,0)
   FONT (12,0,0,700,0,0,0,"Arial")
  }
  TEXT  172, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 5,1, (0,0,0)
   TEXT "$TITLE"
   RECT (1310,1440,1980,1500)
   ALIGN 4
   MARGINS (1,1)
   COLOR (0,0,0)
   FONT (12,0,0,700,0,0,0,"Arial")
   UPDATE 0
  }
  LINE  173, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (128,128,128)
   POINTS ( (1130,1380), (2000,1380) )
   FILL (1,(0,0,0),0)
  }
  LINE  174, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (128,128,128)
   POINTS ( (1130,1440), (2000,1440) )
   FILL (1,(0,0,0),0)
  }
  LINE  175, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (128,128,128)
   POINTS ( (1300,1380), (1300,1500) )
  }
  LINE  176, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (128,128,128)
   POINTS ( (2000,1500), (2000,1240), (1130,1240), (1130,1500), (2000,1500) )
   FILL (1,(0,0,0),0)
  }
  TEXT  177, 0, 0
  {
   PAGEALIGN 10
   TEXT 
"(C)ALDEC. Inc\n"+
"2230 Corporate Circle\n"+
"Henderson, NV 89074"
   RECT (1140,1260,1435,1361)
   MARGINS (1,1)
   COLOR (0,0,0)
   FONT (12,0,0,700,0,0,0,"Arial")
   MULTILINE
  }
  LINE  178, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (128,128,128)
   POINTS ( (1440,1240), (1440,1380) )
  }
  LINE  179, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,4, (0,4,255)
   POINTS ( (1616,1304), (1682,1304) )
   FILL (0,(0,4,255),0)
  }
  LINE  180, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (0,4,255)
   POINTS ( (1585,1300), (1585,1300) )
   FILL (0,(0,4,255),0)
  }
  LINE  181, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,3, (0,4,255)
   POINTS ( (1634,1304), (1650,1264) )
   FILL (0,(0,4,255),0)
  }
  TEXT  182, -4, 0
  {
   PAGEALIGN 10
   OUTLINE 5,0, (49,101,255)
   TEXT "ALDEC"
   RECT (1663,1246,1961,1348)
   MARGINS (1,1)
   COLOR (0,4,255)
   FONT (36,0,0,700,0,1,0,"Arial")
  }
  LINE  183, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,3, (0,4,255)
   POINTS ( (1576,1264), (1551,1327) )
   FILL (0,(0,4,255),0)
  }
  BEZIER  184, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,3, (0,4,255)
   FILL (0,(0,4,255),0)
   ORIGINS ( (1583,1290), (1616,1304), (1583,1315), (1583,1290) )
   CONTROLS (( (1607,1290), (1615,1289)),( (1613,1315), (1610,1315)),( (1583,1307), (1583,1302)) )
  }
  LINE  185, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,4, (0,4,255)
   POINTS ( (1495,1311), (1583,1311) )
   FILL (0,(0,4,255),0)
  }
  LINE  186, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,4, (0,4,255)
   POINTS ( (1502,1294), (1583,1294) )
   FILL (0,(0,4,255),0)
  }
  LINE  187, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (0,4,255)
   POINTS ( (1688,1271), (1511,1271) )
   FILL (0,(0,4,255),0)
  }
  LINE  188, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (0,4,255)
   POINTS ( (1686,1278), (1508,1278) )
   FILL (0,(0,4,255),0)
  }
  LINE  189, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (0,4,255)
   POINTS ( (1700,1286), (1506,1286) )
   FILL (0,(0,4,255),0)
  }
  LINE  190, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (0,4,255)
   POINTS ( (1702,1294), (1510,1294) )
   FILL (0,(0,4,255),0)
  }
  LINE  191, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (0,4,255)
   POINTS ( (1615,1302), (1499,1302) )
   FILL (0,(0,4,255),0)
  }
  LINE  192, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (0,4,255)
   POINTS ( (1680,1311), (1495,1311) )
   FILL (0,(0,4,255),0)
  }
  LINE  193, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (0,4,255)
   POINTS ( (1673,1319), (1492,1319) )
   FILL (0,(0,4,255),0)
  }
  TEXT  194, 0, 0
  {
   PAGEALIGN 10
   TEXT "The Design Verification Company"
   RECT (1482,1336,1934,1370)
   MARGINS (1,1)
   COLOR (0,4,255)
   FONT (12,0,0,700,1,1,0,"Arial")
  }
  LINE  195, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (0,4,255)
   POINTS ( (1667,1327), (1489,1327) )
   FILL (0,(0,4,255),0)
  }
  LINE  196, 0, 0
  {
   PAGEALIGN 10
   OUTLINE 0,1, (0,4,255)
   POINTS ( (1690,1264), (1514,1264) )
   FILL (0,(0,4,255),0)
  }
 }
 
}