lut_mod7_4b.v

来自「数字钟可以说明的具体功能都在文件家中,请仔细参阅,希望大家可以相互学习,共同进步」· Verilog 代码 · 共 42 行

V
42
字号
module LUT_MOD7_4b(in,out);
	input [4:0]in;
	output [1:0]out;
	reg	   [1:0]out;
	
	always @(in)
		case(in)
			0 : out<=0;
			1 : out<=1;
			2 : out<=2;
			3 : out<=3;
			4 : out<=4;
			5 : out<=5;
			6 : out<=6;
			7 : out<=0;
			8 : out<=1;
			9 : out<=2;
			10: out<=3;
			11: out<=4;
			12: out<=5;
			13: out<=6;
			14: out<=0;
			15: out<=1;
			16: out<=2;
			17: out<=3;
			18: out<=4;
			19: out<=5;
			20: out<=6;
			21: out<=0;
			22: out<=1;
			23: out<=2;
			24: out<=3;
			25: out<=4;
			26: out<=5;
			27: out<=6;
			28: out<=0;
			29: out<=1;
			30: out<=2;
			31: out<=3;
			default:out<=0;
		endcase
endmodule		

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?