stopwatchctrl.v

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`timescale 1ns / 100ps

module StopWatchCtrl (ClearCounter, Clk, CE,HoldReset, Holding, RefreshHold, Reset, Running, StartPause);
input   Clk, CE;
input   HoldReset;
input   Reset;
input   StartPause;
output  ClearCounter;
output  Holding;
output  RefreshHold;
output  Running;

wire    Clk;
wire    Reset;
wire    HoldReset;
wire    StartPause;
wire    Running;
wire    Holding;
reg     RefreshHold;
reg     ClearCounter;

// USER DEFINED ENCODED state machine: S
// State codes definitions:
`define S1 2'b00
`define S2 2'b01
`define S3 2'b11

reg [1:0]CurrState_S, NextState_S; 
reg Next_ClearCounter, Next_RefreshHold;

assign {Holding,Running}= CurrState_S;
//--------------------------------------------------------------------
// Machine: S
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (StartPause or HoldReset or CurrState_S)
begin : S_NextState
	// Set default values for outputs and signals
	// ... 
	case (CurrState_S)	// synopsys parallel_case full_case
		`S1:
			if (StartPause==1)
			begin
				NextState_S <= `S2;
				Next_ClearCounter<=1;Next_RefreshHold<=0;
			end
			else if (HoldReset==1)
			begin
				NextState_S <= `S1;
				Next_ClearCounter<=0;Next_RefreshHold<=0;
			end
			else 
			begin
				NextState_S <= `S1;
				Next_ClearCounter<=1;Next_RefreshHold<=0;
			end	
		`S2:
			if (StartPause==1)
			begin
				NextState_S <= `S1;
				Next_ClearCounter<=1;Next_RefreshHold<=0;
			end
			else if (HoldReset==1)
			begin
				NextState_S <= `S3;
				Next_ClearCounter<=1;Next_RefreshHold<=1;
			end
			else 
			begin
				NextState_S <= `S2;
				Next_ClearCounter<=1;Next_RefreshHold<=0;
			end
		`S3:
			if (StartPause==1)
			begin
				NextState_S <= `S3;
				Next_ClearCounter<=1;Next_RefreshHold<=1;
			end
			else if (HoldReset==1)
			begin
				NextState_S <= `S2;
				Next_ClearCounter<=1;Next_RefreshHold<=0;
			end
			else 
			begin
				NextState_S <= `S3;
				Next_ClearCounter<=1;Next_RefreshHold<=0;
			end 
		default:
			begin
				NextState_S <= `S1;
				Next_ClearCounter<=1;Next_RefreshHold<=0;
			end
	endcase
end

//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (negedge Reset , posedge Clk)
begin : S_CurrentState
	if (!Reset)
		begin CurrState_S <=0; ClearCounter<=1;RefreshHold<=0;end
	else if(CE)
		begin 
			CurrState_S <= NextState_S;
			ClearCounter<=Next_ClearCounter;
			RefreshHold<=Next_RefreshHold;
		end
end

endmodule