mmu8xx.c

这是单板上DPRAM的驱动程序

/* @(#) pSOSystem PowerPC/V2.2.2: bsps/devices/powerpc/mmu8xx.c 3.6 97/10/09 10:27:57 */
/***********************************************************************/
/*                                                                     */
/*   MODULE:  bsps/devices/powerpc/mmu8xx.c                            */
/*   DATE:    97/10/09                                                 */
/*   PURPOSE: Memory Managment Unit (MMU) driver module                */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*                                                                     */
/*           Copyright 1991 - 1997, Integrated Systems, Inc.           */
/*                      ALL RIGHTS RESERVED                            */
/*                                                                     */
/*   Permission is hereby granted to licensees of Integrated Systems,  */
/*   Inc. products to use or abstract this computer program for the    */
/*   sole purpose of implementing a product based on Integrated        */
/*   Systems, Inc. products.   No other rights to reproduce, use,      */
/*   or disseminate this computer program, whether in part or in       */
/*   whole, are granted.                                               */
/*                                                                     */
/*   Integrated Systems, Inc. makes no representation or warranties    */
/*   with respect to the performance of this computer program, and     */
/*   specifically disclaims any responsibility for any damages,        */

/*                                                                     */
/*---------------------------------------------------------------------*/
/*                                                                     */
/*   The Memory Managment Unit provides translation of effective       */
/*   addresses generated by the fix-point unit or instruction prefetch */
/*   unit into physical address. The MMU also provides cache control   */
/*   for the split code and data cache (like write-through or write-   */
/*   back policies).                                                   */ 
/*                                                                     */
/***********************************************************************/
#include <bspfuncs.h>
#include <icontrol/mpc8xx.h>
#include <machine.h>
#include "../bsp.h"
#include "board.h"
#include <icontrol/mmu8xx.h>
#include <icontrol/pda8xx.h>

#define	STATIC static

#define LVL1_PAGE_SIZE   0x400000

/***********************************************************************/
/* Local Function Prototypes                                           */
/***********************************************************************/
void MapVir2RealAddr(UCHAR *VirAddr, UCHAR *RealAddr, ULONG Size, 
                            PAGE_T Attributes, ULONG cachePolicy);
void EnableCache(void);
void DisableCache(void);
STATIC void InitMmu(ULONG);
STATIC UCHAR *AllocBlankPage(void);

UCHAR *BspMmuInit(ULONG FreeMemPtr);
void   DisCacheing(UCHAR *VirAddr, ULONG Size, UCHAR Cache);

STATIC void MapVir2RealArea(UCHAR *VirAddr, UCHAR *RealAddr, ULONG Size, 
                            PAGE_T Attributes, ULONG cachePolicy);

/***********************************************************************/
/* Extern functions                                                    */
/***********************************************************************/
extern ULONG GetMachineState(void);
extern void SetMachineState(ULONG Value);
extern void SetCASID(ULONG NewCASID);
extern void ClearTLB(void);
extern ULONG GetIMMR(void);
extern void SetTalkwalkBase(ULONG Segment);
extern void SetIMMUControl(ULONG Value);
extern void SetDMMUControl(ULONG Value);
extern void SetIcacheControl(ULONG Value);
extern void SetDcacheControl(ULONG Value);
extern void ITLBMissHandler(void);
extern void DTLBMissHandler(void);
extern void BspMmuTransOff(void);
extern void BspMmuTransOn(void);
extern void BspMmuDataTransOn(void);
extern void MapRegions(void);
extern void BrdBufDisCacheing();



/***********************************************************************/
/* Global variables                                                    */
/***********************************************************************/
UCHAR     *gNextPageAddr;      	/* Ptr to the next available page */
SEG_T     *gSegAddr; 	       	/* First level descriptor pointer */	
UCHAR	   gMmuState = 0;

/***********************************************************************/
/*                                                                     */
/* UCHAR *BspMmuInit(ULONG) : Initialize the Memory Managment Unit     */
/* Setup mapping of the DRAM, Internal register map, Dual-ported RAM   */
/* (IMMR) and flash region.                                            */
/*                                                                     */
/***********************************************************************/
UCHAR *
BspMmuInit(ULONG FreeMemPtr)
{
	ULONG Addr;
	ULONG Size;

        /* Enable for chips REV A.2 or greater */
        /* 
            It seems that there's a version error in MPC8XX series chips. 
            The version of MPC860C1 is 3.1, but MPC860D3's version number is read as Ver 0.1.
            So I comment it out.           -----by Shan Zhengguang, 7/17/2000
        */
        /*
        if ((GetIMMR() & 0x00FF) <= (REVA | 1))
            return ((UCHAR *)FreeMemPtr);
	*/
	
	/* Initialize the MMU registers */
	InitMmu(FreeMemPtr);

        /* Setup I-TLB and D-TLB Miss Exception Handler */
	SysSetVector(V_ITLB, ITLBMissHandler, VT_DIRECT, 0);
	SysSetVector(V_DTLB, DTLBMissHandler, VT_DIRECT, 0);

	/* Map the memory regions on the ADS8xx board */
	MapRegions();


	BrdBufDisCacheing();

	/* Enable the MMUs, depending on BSP_IMMU flags, both D-MMU  */ 
        /* and I-MMU or D-MMU only                                   */
	EnableMMU();

	/* Enable the Data and Code caches */
	EnableCache();
	return(gNextPageAddr);
}


/***********************************************************************/
/*                                                                     */
/* UCHAR *InitMmu(ULONG): Initialize the MMU registers           */
/*                                                                     */
/* Initialize the MMU registers, segment table descriptors, page table */
/* descriptors and tablewalk handler.                                  */
/***********************************************************************/
STATIC void
InitMmu(ULONG FreeMemPtr)
{
	
	MX_CTR MMUControl;
	ULONG  PageTblAddr;
	int i;


	/* Clear/Invalidate all the TLB entries */
	ClearTLBEntries();
	
        /* Set up the page allocation to start at the FreeMemPtr supplied. */
	PageTblAddr = ALIGN((ULONG) FreeMemPtr, PAGE_SIZE);
        gNextPageAddr = (UCHAR *)(PageTblAddr + PAGE_SIZE);
 
        /* Allocate a page for segment/Level One descriptors */
        gSegAddr = (SEG_T *)AllocBlankPage();
 
        /* Write segment table base in Talkwalk base register */
        SetTalkwalkBase((ULONG)gSegAddr);
 
        /* Current address space to Supervisor ID */
        SetCASID(SUPER_ID);
 
	/* Set the Data and Instruction Access Protection */
	SetDataAccessProt(0xFFFFFFFF);
	SetInstAccessProt(0xFFFFFFFF);

        /* Now, program the I-MMU Control register */
        MMUControl.Word = 0;           /* clear all bits */
        MMUControl.Bit.GroupPMode = 0; /* PowerPC Mode */
        MMUControl.Bit.PagePMode = 0;  /* Page Resolution Protection */
        MMUControl.Bit.CacheDis = 1;   /* Instruction Cache inhibited when
                                         * cache is off */
        MMUControl.Bit.Res4TLBs = 1;   /* Reseved 4 TLBs, modulo 28 entries */
        MMUControl.Bit.PPCSMode = 1;   /* Problem/Privileged from Mx_RPN */
        MMUControl.Bit.TLBIndex = 28;  /* The next TLB load starts at 27 */
        SetIMMUControl(MMUControl.Word);
 
        MMUControl.Bit.CacheMode = 1;  /* Data Cache Write-Thru mode when
                                         * cache is off */
        MMUControl.Bit.TWalkMode = 1;  /* 4K-page hardware assist mode */
        SetDMMUControl(MMUControl.Word);
}

/***********************************************************************/
/*                                                                     */
/* UCHAR *AllocBlankPage(void): Allocates a blank page.                */
/*                                                                     */
/***********************************************************************/
STATIC UCHAR *
AllocBlankPage(void)
{
        UCHAR *TempPagePtr = gNextPageAddr;
 
	if ((ULONG)(gNextPageAddr + PAGE_SIZE) > 
		(ULONG)(BSP_RAM_BASE + RamSize())) 
                SysInitFail("Out of Memory to allocate MMU pages!!!");

        gNextPageAddr += PAGE_SIZE;             /* Next Available page */
        BspBfill(TempPagePtr, PAGE_SIZE, 0);    /* clear out this page */
        return(TempPagePtr);    
}
 
/***********************************************************************/
/*                                                                     */
/* STATIC void MapVir2RealAddr(UCHAR*, UCHAR*, ULONG, PAGE)            */