📄 init.s
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#* @(#) pSOSystem PowerPC/V2.2.2*
#************************************************************************
# *
# MODULE: bsps/fuc8xx/src/init.s_rev *
# DATE: 98/07/03 *
# AUTHOR: Shan Zhengguang *
# PURPOSE: Processor specific initialization module *
# *
#-----------------------------------------------------------------------*
# *
# COPYRIGHT 1998 - 1999, ZHONGXING TELECOM CO.,LTD. *
# ALL RIGHTS RESERVED *
# *
#-----------------------------------------------------------------------*
# REV:
# add initial rccr reg. for use microcode .... py *
#************************************************************************
.include "macros.ia"
.include "board.ia"
#************************************************************************
# External function & variable definitions
#************************************************************************
.extern ppcDECwr
.extern Initial_Sp
.extern InitBoard
.extern SysIcacheInhibit
.extern SysDcacheInhibit
.extern StartBss, FreeMemStart
.extern _CpyDstBeg,_CpyDstEnd,_CpySrcBeg, BspBcopy
.extern HdwInitDRAM
.extern resetSWT
#************************************************************************
# HdwInit: Do startup initialization that can't be done in C. *
# *
# SYNTAX: void HdwInit(void); *
# NOTE: Called from "begin.s", Doesn't return. *
# *
#************************************************************************
.text
.align 2
.globl HdwInit
HdwInit:
li r0,0x0000
LA r1,S_REGISTER_BASE+0x2FF0
#************************************************************************
# Set the MSR - machine check, privileged mode, disable interrupts *
# disable address translation *
#************************************************************************
LA r3,0x00001000
bl ppcMSRwr
#************************************************************************
# Set the decrementer to a very high value *
#************************************************************************
LA r3,DEC_MAX_COUNT
bl ppcDECwr
#************************************************************************
# Inhibit Instruction and Data caches, we'll enable it later if needed *
#************************************************************************
bl SysDcacheInhibit # D cache inhibit
bl SysIcacheInhibit # I cache inhibit
#************************************************************************
# Initialize Core registers
#
# 1. MACHINE STATUS REGISTER (MSR):
# - Machine Check Enable
# - Recoverable Interrupt
#************************************************************************
LA r3, MSR_VAL
mtmsr r3
mtspr SRR1,r3
#************************************************************************
# 2. INSTRUCTION SUPPORT CONTROL REGISTER (ICTRL):
# - Development port trap enable on 3rd instruction watchpoint.
# - Development port trap enable on 4th instruction watchpoint.
#************************************************************************
LA r3, ICTRL_VAL
mtspr ICTRL,r3
#************************************************************************
# 3. DEBUG ENABLE REGISTER (DER):
# - All debug interrupts are disabled
# Note: The default value is 0x00000000, this disables all debug
# enable bits in the DER register. To enable the various
# debug events, set the appropriate bit. For more details
# see page 18-51 an 18-52.
#************************************************************************
LA r3, DER_VAL
mtspr DER,r3
#************************************************************************
# 4. INTERRUPT CAUSE REGISTER (ICR):
# - All the interrupt causing events are off.
#************************************************************************
LA r3, ICR_VAL
mtspr ICR,r3
#------------------------------------------------------------------------
# This delay loop is used to wait all characters in serial port to be
# sent out to avoid some garbage characters when we reset CPM.
#------------------------------------------------------------------------
lis r3, 0x2
delay0:
subi r3,r3,1
cmpwi r3,0
bne delay0
#************************************************************************
# 5. INTERNAL MEMORY MAP REGISTER (IMMR):
# - Upper 16bits of base address of the internal memory map.
# Default address is 0x02B000000
#************************************************************************
LA r3, S_REGISTER_BASE
mtspr IMMR,r3
#************************************************************************
# 6. System Interface Unit (SIU) Module Configuration Register (SIUMCR)
#************************************************************************
or r4,r3,r0 # R4 = Content of IMMR = Memory Base
lwz r3,SIUMCR(r4) # SIUMCR = The old value bitwize
oris r3,r3,0x0060 # ored with 0x00600040
ori r3,r3,0x0040
stw r3,SIUMCR(r4)
# LA r3, SYPCR_VAL # two lines support SWT & bus monitor
# stw r3,SYPCR(r4) # now a fun named stopSWT() supplied.
#************************************************************************
# 7. Unlock and Clear the Reset Status Register (RSR)
#************************************************************************
LA r3, 0x55ccaa33 # Key to gain access to RSR
stw r3, RSKR(r4) # Write key the Reset Status Key reg
LA r3, 0x40000000
stw r3, RSR(r4) # Clear "External Soft Reset" bit
#************************************************************************
# Enable Decrementer
#************************************************************************
li r3,0x0001 # TBSCR = 0x00c2 (16bit register)
sth r3,TBSCR(r4)
LA r3,0x55ccaa33 # Unlock RTCSC
stw r3,RTCSCK(r4) # RTCSCK = 0x55ccaa33 (32bit register)
li r3,0x0102 # RTCSC = 0x01c2 (16bit register)
sth r3,RTCSC(r4)
li r3,0x0002 # PISCR = 0x0082 (16bit register)
sth r3,PISCR(r4)
li r3,0x0000 # Clear SIMASK
stw r3,SIMASK(r4)
#------------------------------------------------------------------------
# Initialize Chip Select 0 for Boot - ROM
#------------------------------------------------------------------------
LA r3, BR0_VAL
stw r3,BR0(r4)
LA r3, OR0_VAL
stw r3,OR0(r4)
#------------------------------------------------------------------------
# Initialize Chip Select 1 for Flash
#------------------------------------------------------------------------
LA r3,OR1_VAL
stw r3,OR1(r4)
LA r3,BR1_VAL
stw r3,BR1(r4)
#------------------------------------------------------------------------
# Initialize Chip Select 2 for SDRAM
#------------------------------------------------------------------------
LA r3,OR2_VAL
stw r3,OR2(r4)
LA r3,BR2_VAL
stw r3,BR2(r4)
#------------------------------------------------------------------------
# Initialize Chip Select 3 for CHP
#------------------------------------------------------------------------
LA r3, OR3_VAL
stw r3,OR3(r4)
LA r3, BR3_VAL
stw r3,BR3(r4)
#------------------------------------------------------------------------
# Initialize Chip Select 4 for MFP
#------------------------------------------------------------------------
LA r3, OR4_VAL
stw r3,OR4(r4)
LA r3, BR4_VAL
stw r3,BR4(r4)
#------------------------------------------------------------------------
# Initialize Chip Select 5 for Board Address
#------------------------------------------------------------------------
LA r3, OR5_VAL
stw r3,OR5(r4)
LA r3, BR5_VAL
stw r3,BR5(r4)
#------------------------------------------------------------------------
# Initialize Chip Select 6 for Board Address
#------------------------------------------------------------------------
LA r3, OR6_VAL
stw r3,OR6(r4)
LA r3, BR6_VAL
stw r3,BR6(r4)
#------------------------------------------------------------------------
# Initialize Chip Select 7 for Board Address
#------------------------------------------------------------------------
LA r3, OR7_VAL
stw r3,OR7(r4)
LA r3, BR7_VAL
stw r3,BR7(r4)
#------------------------------------------------------------------------
# If we are not executing from the BOOT-ROM, skip Mem Controller SDRAM init
#------------------------------------------------------------------------
bl locn00 # LR: current IP
locn00:
mflr r3 # r3: current IP
rlwinm r3,r3,8,24,31
LA r5,CS0_BASE
rlwinm r5,r5,8,24,31
cmplw r3,r5 #
bne locn01
#------------------------------------------------------------------------
# Determine what type of DRAM SIMM is installed and load r5 and r6
# to point to the beginning and end, respectively, of the corresponding
# UPMA initialization table.
#------------------------------------------------------------------------
mr r18,r4
li r3,0x0000 # Clear SIMASK
stw r3,SIMASK(r18)
stw r3,RCCR(r18) # Clear the RISC Config Reg
li r3,0x8001
sth r3,CPCR(r18) # reset CPM
addi r1,r18,0x2ff0 # use DPRAM as stack
bl HdwInitDRAM
bl resetSWT
#------------------------------------------------------------------------
# Clear the DPRAM area which is used as stack.
#------------------------------------------------------------------------
addi r4,r18,0x2000
addi r5,r18,0x3000
li r6,0
1:
stw r6,0(r4)
addi r4,r4,4
cmplw r4,r5
bne 1b
mr r4, r18 # restore r4
locn01:
#------------------------------------------------------------------------
# clear RCCR add by py
#------------------------------------------------------------------------
li r3,0x0000
stw r3,RCCR(r4) # Clear the RISC Config Reg
#------------------------------------------------------------------------
# Set the input clock multiplication factor
#------------------------------------------------------------------------
# lis r3,DEF_PLL_MULT # default PLL mult factor
# stw r3,PLPRCR(r4) # set the PLL register
#-----------------------------------------------------------------------*
# Copy DATA section from FLASH to RAM. *
#-----------------------------------------------------------------------*
LA r18, S_REGISTER_BASE
# LA r3, 0xffffff88 # two lines support SWT & bus monitor
# stw r3,SYPCR(r18) # now a fun named stopSWT() supplied.
LA r19,0x556c
LA r20,0xaa39
# just for resetSWT
LA r3,_CpySrcBeg # Address of Data section in FLASH
LA r4,_CpyDstBeg # Address of Data Section in RAM
LA r5,_CpyDstEnd
subf r5,r4,r5 # r5: # bytes to copy
mflr r17 # Save Link register
# bl BspBcopy # Copy Data section to RAM
#BspBcopy:
cmpwi r5, 0 # if length == 0 : All done
beq done
mtspr 9,r5
aa00:
sth r19,0xE(r18) # now a fun named stopSWT() supplied.
sth r20,0xE(r18) # now a fun named stopSWT() supplied.
#
lbzu r6, 1(r3) # Load a byte with increment
stbu r6, 1(r4) # Store a byte with increment
bc 16,0,aa00 # while len != 0 Loop
#
done:
sync
mtlr r17 # Restore Link Register
####################################################
LA r3, StartBss # r3: address
LA r4, FreeMemStart # r4: first address *not* to be cleared
sub r4, r4, r3 # r4: length
li r5, 0 # r5: value to store (0)
# bl BspBfill # CLear Bss area
#BspBfill:
cmpwi r4, 0 # if length == 0 : All done
beq done1
mtspr 9,r4
aa01:
stbu r5, 1(r3) # Store a byte with increment
sth r19,0xE(r18) # now a fun named stopSWT() supplied.
sth r20,0xE(r18) # now a fun named stopSWT() supplied.
bc 16,0,aa01 # while len != 0 Loop
#
done1:
sync
# LA r3, 0xffffff88 # two lines support SWT & bus monitor
# stw r3,SYPCR(r18) # now a fun named stopSWT() supplied.
####################################################
bl resetSWT
LA r1,Initial_Sp # Set stack pointer
subi r1,r1,16 # need reserving 8 bytes for C
mfmsr r3
ori r3,r3,0x1000
mtmsr r3 # Enable machine-check exceptions
bl InitBoard # Remainder of hardware init
blr # Never executed
.align 2
.globl stopSWT
.end
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