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📄 bdcomm.h

📁 这是单板上DPRAM的驱动程序
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#define	CPCR        0x09c0       /* CPM Command Reg. */
#define 	RCCR        0x09c4       /* RISC COnfihuration Register . */
#define	BRGC1       0x09f0       /* BRG1 Configuration Reg. */
#define	SMCMR1      0x0a82       /* SMC1 Mode Register */
#define	SMCE1       0x0a86       /* SMC1 Event Register */
#define	SMCM1       0x0a8a       /* SMC1 Mask Register */
#define	PBPAR       0x0abc       /* Port B Pin Assignment Reg. */
#define	PBDIR       0x0ab8       /* Port B Data Direction Reg. */
#define	PBODR       0x0ac2       /* Port B Open Drain Reg. */
#define	SIMODE      0x0ae0       /* SI Mode Reg. */
#define	SICR        0x0aec       /* SI Clock Route */

#define	Rxbd        0x2800       /* Rx Buffer Descriptor Offset */
#define	Txbd        0x2808       /* Tx Buffer Descriptor Offset */

#define	Rxbuf       0x2810       /* offset 810 from Dual Port Ram */
#define	Txbuf       0x2820       /* offset 820 from Dual Port Ram */

#define	SMC1RBAS    0x3e80+0x00  /* Rx BD Base Address */
#define	SMC1TBAS    0x3e80+0x02  /* Tx BD Base Address */
#define	SMC1RFCR    0x3e80+0x04  /* Rx Function Code */
#define	SMC1TFCR    0x3e80+0x05  /* Tx Function Code */
#define	SMC1MRBL    0x3e80+0x06  /* Max. Receive Buffer Length */
#define	SMC1RBPTR   0x3e80+0x10  /* Rx Buffer Descriptor Pointer */
#define	SMC1TBPTR   0x3e80+0x20  /* Tx Buffer Descriptor Pointer */
#define	SMC1MAXI    0x3e80+0x28  /* Max. Idle Character */
#define	SMC1BRKL    0x3e80+0x2c  /* Last Received Break Length */
#define	SMC1BRKE    0x3e80+0x2e  /* Receive Break Condition Counter */
#define	SMC1BRKC    0x3e80+0x30  /* Break Count Register  */

/*------------------------------------------------------------------------*/
/* Instruction and Data Cache definition                                  */
/* Note: must use with lis instruction to load into bit 0-15              */
/*------------------------------------------------------------------------*/
#define	CacheUnlockAllCmd   0x0A00   /* Cache Unlock_All command */
#define	CacheDisableCmd     0x0400   /* Cache Disable command */
#define	CacheInvAllCmd      0x0C00   /* Cache Invalidate_All command */
#define	CacheEnableCmd      0x0200   /* DCache_Enable Command */
#define	CacheEnableBit      0x8000   /* Cache Enable bit in I/DC_CST */

struct PinMap
    {
    ULONG available;           /* TRUE or FALSE                  */
    ULONG direction;           /* IN or OUT */
    ULONG port;                /* PORTA, PORTB or PORTC */
    ULONG bit;                 /* 1 - 15 bit that defines the pin */
    ULONG type;                /* GENERAL I/O or INTERNAL to chip */
    ULONG inttype;             /* IANY or IHL */
    };

/*---------------------------------------------------------------------*/
/* Number of baudrate generators (per QUICC, imposed by hardware)      */
/*---------------------------------------------------------------------*/
#define MAX_BRG         4

#define CR_INITRXTX     0
#define BRGC_BRGCLK     0

/*---------------------------------------------------------------------*/
/* SCC Generic Parameter RAM (Dual-Port memory) definition             */
/*---------------------------------------------------------------------*/
#define SCC_BD_TFCR   0x15  /* Motorola order, FC=Supervisor Data DMA cycle */
#define SCC_BD_RFCR   0x15  /* Motorola order, FC=Supervisor Data DMA cycle */

/*---------------------------------------------------------------------*/
/* PORT A - C pin configuration                                        */
/*---------------------------------------------------------------------*/
#define IN  1
#define OUT 2

#define PORTA 1
#define PORTB 2
#define PORTC 3
#define PORTD 4

#define GENERAL  1            /* GENERAL I/O pin */
#define INTERNAL 2            /* INTERNAL to 68360 */

#define IANY 1                /* Any change interrupts (PORTC only) */
#define IHL  2                /* High to low change (PORTC only) */

#ifndef MAX_LEADS
#define MAX_LEADS 9
#endif

/*---------------------------------------------------------------------*/
/* leads to the outside world (some may not be supported)              */
/*---------------------------------------------------------------------*/
#define LEAD_RXD    0
#define LEAD_TXD    1
#define LEAD_TCLK   2
#define LEAD_RCLK   3
#define LEAD_DTR    4
#define LEAD_DSR    5
#define LEAD_RTS    6
#define LEAD_CTS    7
#define LEAD_CD     8

static struct PinMap PinMap[MAX_SCC][MAX_LEADS] =
{
    /*-----------------------------------------------------------------*/
    /* Master Ports                                                    */
    /*-----------------------------------------------------------------*/

    /*-----------------------------------------------------------------*/
    /* SCC1  avail,  dir, port,   bit,    type,     interrupt          */
    /*-----------------------------------------------------------------*/
    /*RXD1*/ FALSE,   0,  0,        0,          0,     0, /*RXD1*/
    /*TXD1*/ FALSE,   0,  0,        0,          0,     0, /*TXD1*/
    /*TCLK1*/FALSE,   0,  0,        0,          0,     0, /*TCLK1*/
    /*RCLK1*/FALSE,   0,  0,        0,          0,     0, /*RCLK1*/

    /*DTR1*/ FALSE,   0,  0,        0,          0,     0, /*DTR1*/
    /*DSR1*/ FALSE,   0,  0,        0,          0,     0, /*DSR1*/
    /*RTS1*/ FALSE,   0,  0,        0,          0,     0, /*RTS1*/

    /*CTS1*/ FALSE,   0,  0,        0,          0,     0, /*CTS1*/
    /*CD1*/  FALSE,   0,  0,        0,          0,     0, /*CD1*/

    /*-----------------------------------------------------------------*/
    /* SCC2  avail,  dir, port,   bit,    type,     interrupt          */
    /*-----------------------------------------------------------------*/
    /*RXD2*/ FALSE,  IN,  PORTA,  BIT2,   INTERNAL,    0,  /*RXD2*/
    /*TXD2*/ FALSE,  IN,  PORTA,  BIT3,   INTERNAL,    0,  /*TXD2*/
    /*TCLK2*/FALSE,  OUT, PORTA,  BIT10,  INTERNAL,    0,  /*TCLK2*/
    /*RCLK2*/FALSE,  OUT, PORTA,  BIT8,   INTERNAL,    0,  /*RCLK2*/

    /*DTR2*/ FALSE,  0,  0,        0,          0,     0, /*DTR2*/
    /*DSR2*/ FALSE,  0,  0,        0,          0,     0, /*DSR2*/

    /*RTS2*/ FALSE,  IN,  PORTC,  BIT1,   GENERAL,     0,  /*RTS2*/
    /*CTS2*/ FALSE,  IN,  PORTC,  BIT6,   GENERAL,  IANY,  /*CTS2*/
    /*CD2*/  FALSE,  IN,  PORTC,  BIT7,   GENERAL,  IANY,  /*CD2*/

    /*-----------------------------------------------------------------*/
    /* SCC3  avail,  dir, port,   bit,    type,     interrupt          */
    /*-----------------------------------------------------------------*/
    /*RXD3*/ FALSE,   0,  0,        0,          0,     0, /*RXD3*/
    /*TXD3*/ FALSE,   0,  0,        0,          0,     0, /*TXD3*/
    /*TCLK3*/FALSE,   0,  0,        0,          0,     0, /*TCLK3*/
    /*RCLK3*/FALSE,   0,  0,        0,          0,     0, /*RCLK3*/

    /*DTR3*/ FALSE,   0,  0,        0,          0,     0, /*DTR3*/
    /*DSR3*/ FALSE,   0,  0,        0,          0,     0, /*DSR3*/
    /*RTS3*/ FALSE,   0,  0,        0,          0,     0, /*RTS3*/

    /*CTS3*/ FALSE,   0,  0,        0,          0,     0, /*CTS3*/
    /*CD3*/  FALSE,   0,  0,        0,          0,     0, /*CD3*/

    /*-----------------------------------------------------------------*/
    /* SCC4  avail,  dir, port,   bit,    type,     interrupt          */
    /*-----------------------------------------------------------------*/
    /*RXD4*/ FALSE,   0,  0,        0,          0,     0, /*RXD4*/
    /*TXD4*/ FALSE,   0,  0,        0,          0,     0, /*TXD4*/
    /*TCLK4*/FALSE,   0,  0,        0,          0,     0, /*TCLK4*/
    /*RCLK4*/FALSE,   0,  0,        0,          0,     0, /*RCLK4*/

    /*DTR4*/ FALSE,   0,  0,        0,          0,     0, /*DTR4*/
    /*DSR4*/ FALSE,   0,  0,        0,          0,     0, /*DSR4*/
    /*RTS4*/ FALSE,   0,  0,        0,          0,     0, /*RTS4*/

    /*CTS4*/ FALSE,   0,  0,        0,          0,     0, /*CTS4*/
    /*CD4*/  FALSE,   0,  0,        0,          0,     0, /*CD4*/
};

/* Level-Two(Page) Descriptor Format */
/* E - Executable,    N - No Access,    W - ReadWritable,   R - ReadOnly */
/* 1 - Super,Inst,    2 - User,Inst,    3 - Super,Data,     4 - User,Data */
#define PAGE_PP_ENWN 0x000
#define PAGE_PP_EEWR 0x400
#define PAGE_PP_EEWW 0x800
#define PAGE_PP_EERR 0xC00
/* Encoding */
#define PAGE_EN_PPC  0x000
#define PAGE_EN_EXT  0x200
/* Changable */
#define PAGE_UNCHANGE 0x000
#define PAGE_CHANGE   0x100
/* Hit */
#define PAGE_HIT_SUPR 0x080
#define PAGE_HIT_USER 0x040
#define PAGE_HIT_BOTH 0x0C0
/* Size */
#define PAGE_SIZE_4K 0x000
#define PAGE_SIZE_8K 0x008
/* CI */
#define PAGE_CACHE_DISABLE 0x002
#define PAGE_CACHE_ENABLE  0x000
/* V */
#define PAGE_INVALID 0x0
#define PAGE_VALID   0x1


/* ------------------------------------------------------------------------*/ /*
    Next Fucntions and Structures MUST be defined in every board.c
*/ /* ----------------------------------------------------------------------- */
#define MAX_IOI_ENTRIES 80
typedef const struct tagIOIPinMap{
    int available;  /* TRUE, FALSE */
    int port;	    /* PORTA,PORTB,PORTC,PORTD,IRQ*/
    int bit;	    /* BIT[0:31] */
    int par;        /* Pin Assignment Register, 1,Special fun, 0 General fun */
    int dir;	    /* direction 1=1, 0=0 */
    int odr;	    /* open drain 0=TTL, 1=OPEN-DRA0 */
    int so;         /* special option */
    int inttype;    /* interrupt */
    int dat;     /* if port is out, outdat=1,or, 0 */
   }IOIPinMapStruct;
extern IOIPinMapStruct IOIPinMap[MAX_IOI_ENTRIES];

extern void BoardSpecInit(void);           /* It will be called at board.c */
extern void InitTDM(void);                 /* It will be called at board.c */
extern void InitSIMODE(void); 
extern void InitIOMap(void); 
extern void SetLED(unsigned long led,int status);
extern void HdwInitDRAM(void);   /* This function will be called in init.s */
extern ULONG GetDefaultIP(void);   
extern ULONG GetBoardID(void);     /* Get Board ID, like address ,etc */
extern void LanEnable(void);	/* Enable Lan operation */
extern void ExceptionHandle(void); 

/* End of define */

#endif	/* _BDCOMM_H_ */

#if __cplusplus
}
#endif

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