📄 bdcomm.h
字号:
# define SET_VAL(port,val,mask) \
if(port==PORTA)SET_PA_VAL(val,mask); \
else if(port=PORTB)SET_PB_VAL(val,mask); \
else if(port=PORTC)SET_PC_VAL(val,mask); \
else if(port=PORTD)SET_PD_VAL(val,mask);
# define SET_PORT_BIT(port,bit,val) \
if(port==PORTA)SET_PA_BIT(bit,val); \
else if(port=PORTB)SET_PB_BIT(bit,val); \
else if(port=PORTC)SET_PC_BIT(bit,val); \
else if(port=PORTD)SET_PD_BIT(bit,val);
#if 0
#define SET_BITS(port,portsize,mask,dat) { \
if(portsize==32)REG32(port)=(REG32(port)&(~mask))|(mask&dat); \
else if(portsize==16)REG16(port)=(REG16(port)&(~mask))|(mask&dat); \
else REG8(port)=(REG8(port)&(~mask))|(mask&dat); }
#endif
#define IFDESCR "MPC8xx SCC1 LAN"
/*---------------------------------------------------------------------*/
/* This hash define controls which tick timer will be used as the */
/* pSOS+ timer. If it is defined as YES (default) the decrementer on */
/* the processor will be used, otherwise the 8254 compatible timer will*/
/* be the pSOS+ timer. */
/*---------------------------------------------------------------------*/
#define DEC_TICK_TIMER YES
#define TMBASE_PMONT_TIMER YES
/*---------------------------------------------------------------------*/
/* Overhead and rounding value that is used in the final */
/* calculation of the rtcDecTimeConst. */
/*---------------------------------------------------------------------*/
#define BD_RTC_ADJUST_COUNT 0 /* This goes in board.h */
# define BD_VALIDATE_TICK2SEC (anchor->psosct->kc_ticks2sec == 0)
/***********************************************************************/
/* Motorola Microcode present. */
/***********************************************************************/
#define BD_MICROCODE_PRESENT NO /* Yes if microcode is present */
/***********************************************************************/
/* Buffer descriptors used for ethernet and serial channels */
/***********************************************************************/
#define BD_SCC_TX_BDS_ROM BSP_LAN1_PKB_ROM /* Num of Eth Tx BDs for ROM */
#define BD_SCC_RX_BDS_ROM BSP_LAN1_PKB_ROM /* Num of Eth receive BDs */
#define BD_SCC_TXHDRS_ROM (BD_SCC_TX_BDS_ROM)
#define BD_SCC_TX_BDS BSP_LAN1_PKB /* Num of Eth Tx BDs for RAM */
#define BD_SCC_RX_BDS BSP_LAN1_PKB /* Num of Eth receive BDs */
#define BD_SCC_TXHDRS (BD_SCC_TX_BDS)
#define BD_SMC_BDS 10 /* Num of BDs used for serial channel */
/***********************************************************************/
/* Buffer Descriptor offsets */
/***********************************************************************/
#define BD_BUF_DESC_OFF 0
/* Board revision bits */
# define BREV_NUM_MASK 0x008B0000
# define KBYTE 1024
# define MBYTE KBYTE*KBYTE
#define E_REGISTER_BASE S_REGISTER_BASE
#define M_REGISTER_BASE S_REGISTER_BASE
/* #define BD_DPRAM_BASE_ADDR 0x21000000 */ /* DPRAM base address */
#define BD_DPRAM_OFF 0x00000000 /* Dpram offset address */
#define BD_DPRAM_SIZE (5*KBYTE) /* DPRAM size */
#define BD_IO_SIZE 0x00006000 /* Size of IO memory map */
/***********************************************************************/
/* Vector assignments */
/* */
/* Communication Processor Module Interrupts */
/***********************************************************************/
#define CPM_VECT_BASE 0
#define CPM_IRQ_LEVEL 4
#define V_ERROR (0x00 + CPM_VECT_BASE)
#define V_PC4 (0x01 + CPM_VECT_BASE)
#define V_PC5 (0x02 + CPM_VECT_BASE)
#define V_SMC2 (0x03 + CPM_VECT_BASE)
#define V_PIP V_SMC2
#define V_SMC1 (0x04 + CPM_VECT_BASE)
#define V_SPI (0x05 + CPM_VECT_BASE)
#define V_PC6 (0x06 + CPM_VECT_BASE)
#define V_TIMER4 (0x07 + CPM_VECT_BASE)
#define V_PC7 (0x09 + CPM_VECT_BASE)
#define V_PC8 (0x0A + CPM_VECT_BASE)
#define V_PC9 (0x0B + CPM_VECT_BASE)
#define V_TIMER3 (0x0C + CPM_VECT_BASE)
#define V_PC10 (0x0E + CPM_VECT_BASE)
#define V_PC11 (0x0F + CPM_VECT_BASE)
#define V_I2C (0x10 + CPM_VECT_BASE)
#define V_RISC_TIMERS (0x11 + CPM_VECT_BASE)
#define V_TIMER2 (0x12 + CPM_VECT_BASE)
#define V_IDMA2 (0x14 + CPM_VECT_BASE)
#define V_IDMA1 (0x15 + CPM_VECT_BASE)
#define V_SDMA_BUSERR (0x16 + CPM_VECT_BASE)
#define V_PC12 (0x17 + CPM_VECT_BASE)
#define V_PC13 (0x18 + CPM_VECT_BASE)
#define V_TIMER1 (0x19 + CPM_VECT_BASE)
#define V_PC14 (0x1A + CPM_VECT_BASE)
#define V_SCC4 (0x1B + CPM_VECT_BASE)
#define V_SCC3 (0x1C + CPM_VECT_BASE)
#define V_SCC2 (0x1D + CPM_VECT_BASE)
#define V_SCC1 (0x1E + CPM_VECT_BASE)
#define V_PC15 (0x1F + CPM_VECT_BASE)
#define CPM_VECT_END (0x1F + CPM_VECT_BASE)
/*------------------------------------------------------------------------*/
/* vector numbers for the SIU IRQ0 to IRQ7 and ILVL0 to ILVL7 */
/*------------------------------------------------------------------------*/
#define SIU_VECT_BASE (CPM_VECT_END + 1)
#define V_SIU_IRQ0 (SIU_VECT_BASE + 0)
#define V_SIU_LVL0 (SIU_VECT_BASE + 1)
#define V_SIU_IRQ1 (SIU_VECT_BASE + 2)
#define V_SIU_LVL1 (SIU_VECT_BASE + 3)
#define V_SIU_IRQ2 (SIU_VECT_BASE + 4)
#define V_SIU_LVL2 (SIU_VECT_BASE + 5)
#define V_SIU_IRQ3 (SIU_VECT_BASE + 6)
#define V_SIU_LVL3 (SIU_VECT_BASE + 7)
#define V_SIU_IRQ4 (SIU_VECT_BASE + 8)
#define V_SIU_LVL4 (SIU_VECT_BASE + 9)
#define V_SIU_IRQ5 (SIU_VECT_BASE + 10)
#define V_SIU_LVL5 (SIU_VECT_BASE + 11)
#define V_SIU_IRQ6 (SIU_VECT_BASE + 12)
#define V_SIU_LVL6 (SIU_VECT_BASE + 13)
#define V_SIU_IRQ7 (SIU_VECT_BASE + 14)
#define V_SIU_LVL7 (SIU_VECT_BASE + 15)
#define SIU_VECT_END (SIU_VECT_BASE + 31)
/*------------------------------------------------------------------------*/
/* PCMCIA vectors (for interrupts from PCMCIA interface . */
/*------------------------------------------------------------------------*/
#define PCMCIA_VECT_BASE (SIU_VECT_END + 1)
#define PCMCIA_VECT_END (PCMCIA_VECT_BASE + 31)
/*------------------------------------------------------------------------*/
/* keep this definition for some old code. */
/*------------------------------------------------------------------------*/
#define V_EXT_INT V_SIU_IRQ0
/*------------------------------------------------------------------------*/
/* TLB missing exceptions. */
/*------------------------------------------------------------------------*/
#ifdef V_ITLB
#undef V_ITLB
#define V_ITLB 0x1100
#endif
#define V_DTLB 0x1200
#define V_ITLB_ERR 0x1300
#define V_DTLB_ERR 0x1400
/*------------------------------------------------------------------------*/
/* On-Chip Core Register Definitions */
/*------------------------------------------------------------------------*/
#define ICR 148 /* Interrupt Cause Register */
#define ICTRL 158 /* Instruction Control Register */
#define DER 149 /* Debug Enable Register */
#define DPDR 630 /* Development Port Data Register */
#define IMMR 638 /* Internal I/O base register */
/*------------------------------------------------------------------------*/
/* Core register initialization values */
/*------------------------------------------------------------------------*/
#define MSR_VAL 0x00001002 /* Machine status register value */
#define ICTRL_VAL 0x00000006 /* ICTRL initiali value */
#define DER_VAL 0x00000000 /* Debug Enable register control word */
#define ICR_VAL 0x00000000 /* Interrupt cause register value */
#define SYPCR_VAL1 0xFFFFFF8F /* BusMonitor Enable, SoftwareWatchdog Enable */
#define SYPCR_VAL 0xFFFFFF88 /* BusMonitor Enable,SoftwareWatchdog Disable */
#define DRAM_DELAY 0x00000379 /* DRAM delay count */
#define DRAM_PATTERN 0x12345678 /* DRAM test loop pattern */
#define DEC_MAX_COUNT 0x7FFFFFFF /* Decrementer maximum value */
/*------------------------------------------------------------------------*/
/* Input clock multiplication factor used to program the PLL conrtol */
/* register (PLPRCR). The input clock is normally either 4Mhz or 32.768KHz*/
/* Format is following: 0xMMM0 */
/* where MMM = Multiplication factor - 1 */
/*------------------------------------------------------------------------*/
#define DEF_PLL_MULT 0x4C40
/*------------------------------------------------------------------------*/
/* On-Chip Register Offset Definitions */
/* All these registers are offset from the pointer pointed to */
/* by the IMMR in MPC821/860. */
/*------------------------------------------------------------------------*/
#define SIUMCR 0x000 /* SIU Module configuration */
#define SYPCR 0x004 /* SIU System Protection Control */
#define SIMASK 0x014 /* SI Mask Register */
#define SDCR 0x030 /* SDMA Configuration Register */
#define BR0 0x100 /* Base Register 0 */
#define OR0 0x104 /* Option Register 0 */
#define BR1 0x108 /* Base Register 1 */
#define OR1 0x10C /* Option Register 1 */
#define BR2 0x110 /* Base Register 2 */
#define OR2 0x114 /* Option Register 2 */
#define BR3 0x118 /* Base Register 2 */
#define OR3 0x11C /* Option Register 2 */
#define BR4 0x120 /* Base Register 4 */
#define OR4 0x124 /* Option Register 4 */
#define BR5 0x128 /* Base Register 2 */
#define OR5 0x12C /* Option Register 2 */
#define BR6 0x130 /* Base Register 2 */
#define OR6 0x134 /* Option Register 2 */
#define BR7 0x138 /* Base Register 2 */
#define OR7 0x13C /* Option Register 2 */
#define MCR 0x168 /* Memory Command */
#define MAMR 0x170 /* Machine A Mode Register */
#define MPTPR 0x17A /* Memory Periodic Timer Prescaler */
#define MDR 0x17C /* Memory Data */
#define TBSCR 0x200 /* Time Base Status and Control Register */
#define RTCSC 0x220 /* Real Timer Clock Status and Control */
#define PISCR 0x240 /* PIT Status and Control */
#define PLPRCR 0x284 /* PLL, Low Power and Reset Control Reg */
#define RSR 0x288 /* Reset Status register */
#define RSKR 0x388 /* Reset Status Key register */
#define RTCSCK 0x320 /* Real Timer Clock Status and Ctrl Key */
#define CICR 0x0940 /* CP Interrupt Configuration Register */
#define CIPR 0x0944 /* CP Interrupt Pending Register */
#define CIMR 0x0948 /* CP Interrupt Mask Register */
#define PCPAR 0x0962 /* Port C Pin Assignment Reg. */
#define PCDIR 0x0960 /* Port C Data Direction Reg. */
#define PCSO 0x0964 /* Port C Special Option */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -