📄 bdcomm.h
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/* @(#) pSOSystem PowerPC/V2.2.2*/
/***********************************************************************/
/* */
/* MODULE: bsps/ads8xx/src/board.h */
/* DATE: 98/7/1 */
/* AUTHOR: Shan Zhengguang */
/* PURPOSE: Board specific information. This module should include */
/* all base device addresses and board specific macros. */
/* */
/*---------------------------------------------------------------------*/
/* */
/* Copyright 1998-1999, ZHONGXING TELECOM CO.,LTD. */
/* ALL RIGHTS RESERVED */
/* */
/*---------------------------------------------------------------------*/
/* */
/***********************************************************************/
#if __cplusplus
extern "C" {
#endif
#ifndef _BDCOMM_H_
#define _BDCOMM_H_
# include "bsp.h"
# include "src/arch.h"
# include <icontrol/pda8xx.h>
# include <icontrol/mpc8xx.h>
# include "comm_pub.h"
#define USE_UNCACHE_SECTION
#pragma section UNCACHE ".uncachedata" ".uncachedata2" far-absolute RW
extern unsigned long PBMap,PBMask;
extern unsigned short PAMap,PAMask;
extern unsigned short PCMap,PCMask;
extern unsigned short PDMap,PDMask;
#define IRQ1_MASK_BIT 2
#define IRQ1_PENDING_BIT 2
#define IRQ1_SIEL_BIT 2
#define IRQ2_MASK_BIT 4
#define IRQ2_PENDING_BIT 4
#define IRQ2_SIEL_BIT 4
#define IRQ3_MASK_BIT 6
#define IRQ3_PENDING_BIT 6
#define IRQ3_SIEL_BIT 6
#define IRQ4_MASK_BIT 8
#define IRQ4_PENDING_BIT 8
#define IRQ4_SIEL_BIT 8
#define IRQ5_MASK_BIT 10
#define IRQ5_PENDING_BIT 10
#define IRQ5_SIEL_BIT 10
#define IRQ6_MASK_BIT 12
#define IRQ6_PENDING_BIT 12
#define IRQ6_SIEL_BIT 12
#define IRQ7_MASK_BIT 14
#define IRQ7_PENDING_BIT 14
#define IRQ7_SIEL_BIT 14
#ifdef ALIGN
#undef ALIGN
#endif
#define ALIGN(addr, boundary) (((ULONG)(addr)+(ULONG)(boundary)-1) \
& ~((ULONG)(boundary)-1))
#define S_PortDDataDirReg REG16(S_REGISTER_BASE + 0x970)
#define S_PortDPinAssgmntReg REG16(S_REGISTER_BASE + 0x972)
#define S_PortDDataReg REG16(S_REGISTER_BASE + 0x976)
/*---------------------------------------------------------------------*/
/* General Definitions */
/*---------------------------------------------------------------------*/
#ifndef REG8
#define REG8(addr) *((volatile UCHAR *) (addr))
#define REG16(addr) *((volatile USHORT *) (addr))
#define REG32(addr) *((volatile ULONG *) (addr))
#endif
/*---------------------------------------------------------------------*/
/* External Function Declarations */
/* Cache Management Routines */
/*---------------------------------------------------------------------*/
extern void SysIcacheInit(void);
extern void SysDcacheInit(ULONG dCacheMode);
extern void SysDcacheFlush(void *offset, ULONG length);
extern void SysIcacheInv(void *offset, ULONG length);
extern void SysDcacheInv(void *offset, ULONG length);
extern ULONG SysDcacheInhibit(void);
extern void SysIcacheInhibit(void);
/*---------------------------------------------------------------------*/
/* MMU Related Functions */
/*---------------------------------------------------------------------*/
extern void ItlbMissHndlr(void);
extern void DLStlbMissHndlr(void);
extern void ppcBATset(ULONG type, ULONG num, ULONG Uval, ULONG Lval);
extern ULONG ppcSEGget(ULONG segNum);
extern void ppcSEGSset(void);
extern void BspMmuTransOn(void);
extern void BspMmuTransOff(void);
/*---------------------------------------------------------------------*/
/* Processor Related Functions */
/*---------------------------------------------------------------------*/
extern ULONG ppcMSRrd(void);
extern ULONG ppcPVRrd(void);
extern ULONG ppcDECrd(void);
extern void ppcDECwr(ULONG);
extern void ppcMSRwr(ULONG);
extern unsigned long getTBL(void);
extern unsigned long getTBU(void);
/*---------------------------------------------------------------------*/
/* BSP Utility functions */
/*---------------------------------------------------------------------*/
extern void BspBcopy(UCHAR *srcAddr, UCHAR *destAddr, ULONG len);
extern void BspBfill(UCHAR *baseAddr, ULONG length, UCHAR fillVal);
extern ULONG ppc1stbit1(ULONG);
/*---------------------------------------------------------------------*/
/* Perform PowerPC specific sanity checks */
/*---------------------------------------------------------------------*/
#if ((BRD_DCACHE == YES) && (BSP_MMU == NO))
#error "Must enable the MMU for Data Cache Support"
#endif
/*---------------------------------------------------------------------*/
/* Possible input clock frequencies on the FUC8xx board */
/*---------------------------------------------------------------------*/
#define BD_32KHZ_INPUT 32768 /* 32 KHz input clock */
#define BD_4MHZ_INPUT 4000000 /* 4 MHz input clock */
#define BD_5MHZ_INPUT 5000000 /* 5 MHz input clock */
/*---------------------------------------------------------------------*/
/* Selectable CPU frequencies (assuming max is 50Mhz), with the 4Mhz */
/* or a 5Mhz crystal installed. */
/*---------------------------------------------------------------------*/
#define BD_CPU_25MHZ 25 /* CPU runs at 25Mhz */
#define BD_CPU_40MHZ 40 /* CPU runs at 40Mhz */
#define BD_CPU_50MHZ 50 /* CPU runs at 50Mhz */
/*---------------------------------------------------------------------*/
/* Total number of QUICCS in the system */
/*---------------------------------------------------------------------*/
#define MAX_QUICCS 1
#define MAX_SCC 4
#define MAX_SMC 2
#define BD_HAS_SLAVE 0
#define LAN_PORT 0
#define SMC1_CHAN 0
#define SMC2_CHAN 1
#define BD_SIZE_OF_DCACHE 4*KBYTE /* Data cache size on MPC860 */
#define BD_SIZE_OF_ICACHE 4*KBYTE /* Instruction cache size on MPC860 */
#define CACHE_LINE_SIZE 0x10 /* Line of Cache */
#define IO_MAP_MASK 0xffff0000 /* Mask for IO mem map */
#define CPU_REV_MASK 0x000000FF /* Mask for CPU revision */
/*---------------------------------------------------------------------*/
/* The following defines specify cache & snoop capabilities of the */
/* hardware and the mode of operation in pSOSystem, i.e. cache */
/* disabled, instruction cache enabled only and both instruction and */
/* data caches enabled. */
/* */
/* THE FOLLOWING THREE SETS OF DEFINES ARE REPEATED IN cpuarch.a. THEIR*/
/* CONSISTENCY MUST BE MAINTAINED BETWEEN THE TWO FILES. */
/* */
/* Specify the presence of Caches. */
/*---------------------------------------------------------------------*/
#define BRD_ICACHE YES /* Instruction Cache PRESENT */
#define BRD_DCACHE YES /* Data Cache PRESENT */
/*---------------------------------------------------------------------*/
/* Data cache write policy selection. */
/* */
/* To select write-back policy, set the define "BRD_DCACHE_WRITE_THRU" */
/* to "NO". If set to "YES" then, write-through policy is selected. */
/*---------------------------------------------------------------------*/
#define BRD_DCACHE_WRITE_THRU NO /* Cache Write policy */
# define SPLX(A) { unsigned long ilev=splx(1); A; splx(ilev); }
# define SET_BIT(a,bit,w) SPLX((a)|=(1L<<(w-bit-1)))
# define CLR_BIT(a,bit,w) SPLX((a)&=(~(1L<<(w-bit-1))))
# define SET_PA_VAL(val,mask) SPLX(\
PAMap=(((S_PortADataReg&~PAMask)|(PAMap&PAMask))&~(mask))|((val)&(mask));\
S_PortADataReg=PAMap; )
# define SET_PA_BIT(bit,val) SET_PA_VAL(((val)?1:0)<<(15-(bit)),1<<(15-(bit)))
# define GET_PA_BIT(bit) (((1<<(15-(bit)))&S_PortADataReg)?1:0)
# define GET_PA_VAL(mask) ((mask)&S_PortADataReg)
# define INV_PA_BIT(bit) SPLX(\
PAMap=((S_PortADataReg&~PAMask)|(PAMap&PAMask))^(1<<(15-(bit)));\
S_PortADataReg=PAMap; )
# define SET_PB_VAL(val,mask) SPLX(\
PBMap=(((S_PortBDataReg&~PBMask)|(PBMap&PBMask))&~(mask))|((val)&(mask));\
S_PortBDataReg=PBMap; )
# define SET_PB_BIT(bit,val) SET_PB_VAL(((val)?1:0)<<(31-(bit)),1<<(31-(bit)))
# define GET_PB_BIT(bit) (((1<<(31-(bit)))&S_PortBDataReg)?1:0)
# define GET_PB_VAL(mask) ((mask)&S_PortBDataReg)
# define INV_PB_BIT(bit) SPLX(\
PBMap=((S_PortBDataReg&~PBMask)|(PBMap&PBMask))^(1<<(31-(bit)));\
S_PortBDataReg=PBMap; )
# define SET_PC_VAL(val,mask) SPLX(\
PCMap=(((S_PortCDataReg&~PCMask)|(PCMap&PCMask))&~(mask))|((val)&(mask));\
S_PortCDataReg=PCMap; )
# define SET_PC_BIT(bit,val) SET_PC_VAL(((val)?1:0)<<(15-(bit)),1<<(15-(bit)))
# define GET_PC_BIT(bit) (((1<<(15-(bit)))&S_PortCDataReg)?1:0)
# define GET_PC_VAL(mask) ((mask)&S_PortCDataReg)
# define INV_PC_BIT(bit) SPLX(\
PCMap=((S_PortCDataReg&~PCMask)|(PCMap&PCMask))^(1<<(15-(bit)));\
S_PortCDataReg=PCMap; )
# define SET_PD_VAL(val,mask) SPLX(\
PDMap=(((S_PortDDataReg&~PDMask)|(PDMap&PDMask))&~(mask))|((val)&(mask));\
S_PortDDataReg=PDMap; )
# define SET_PD_BIT(bit,val) SET_PD_VAL(((val)?1:0)<<(15-(bit)),1<<(15-(bit)))
# define GET_PD_BIT(bit) (((1<<(15-(bit)))&S_PortDDataReg)?1:0)
# define GET_PD_VAL(mask) ((mask)&S_PortDDataReg)
# define INV_PD_BIT(bit) SPLX(\
PDMap=((S_PortDDataReg&~PDMask)|(PDMap&PDMask))^(1<<(15-(bit)));\
S_PortDDataReg=PDMap; )
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