ds21q50.h

这是单板上DPRAM的驱动程序

#ifndef _CMM_213q50_H
#define _CMM_213q50_H

#define SDB_DS21Q50  340000
#ifndef UCHAR
#define UCHAR unsigned char
#endif

#define SDC_DS21Q50_REMOTE_LOOPBACK        (SDB_DS21Q50+0)
#define SDC_DS21Q50_REMOTE_UNLOOPBACK      (SDB_DS21Q50+1)
#define SDC_DS21Q50_LOCAL_LOOPBACK         (SDB_DS21Q50+2)
#define SDC_DS21Q50_LOCAL_UNLOOPBACK       (SDB_DS21Q50+3)
//#define SDC_DS21Q50_POWERUP                (SDB_DS21Q50+4)
#define SDC_DS21Q50_FRAMER_LOOPBACK        (SDB_DS21Q50+5)
#define SDC_DS21Q50_FRAMER_UNLOOPBACK      (SDB_DS21Q50+6)
#define SDC_DS21Q50_SETSDH                 (SDB_DS21Q50+7)
#define SDC_DS21Q50_UNSETSDH               (SDB_DS21Q50+8)
#define SDC_DS21Q50_GET_ID                 (SDB_DS21Q50+9)
#define SDC_DS21Q50_GET_CODE_VILATION_COUNT (SDB_DS21Q50+10)
#define SDC_DS21Q50_GET_CRC_COUNT          (SDB_DS21Q50+11)
#define SDC_DS21Q50_GET_ERR_COUNT          (SDB_DS21Q50+12)
#define SDC_DS21Q50_GETWARNING             (SDB_DS21Q50+13)

/*--------SR1-----------------*/
/*#define SDE_DS21Q50_RSA1     0X80
#define SDE_DS21Q50_RDMA     0X40
#define SDE_DS21Q50_RSA0     0X20
#define SDE_DS21Q50_RSLIP    0x10
#define SDE_DS21Q50_RUA1     0X8
#define SDE_DS21Q50_RRA      0x4
#define SDE_DS21Q50_RCL      0x2
#define SDE_DS21Q50_RLOS     0x1*/
/*--------SR1-----------------*/

/*--------SR2-----------------*/
/*#define SDE_DS21Q50_RMF      0X80
#define SDE_DS21Q50_RAF      0X40
#define SDE_DS21Q50_TMF      0X20
#define SDE_DS21Q50_SEC      0x10
#define SDE_DS21Q50_TAF      0X8
#define SDE_DS21Q50_LOTC     0x4
#define SDE_DS21Q50_RCMF     0x2
#define SDE_DS21Q50_TSLIP    0x1*/
/*--------SR2-----------------*/

/*--------RIR-----------------*/
/*#define SDE_DS21Q50_TESF     0X80
#define SDE_DS21Q50_TESE     0X40
#define SDE_DS21Q50_JALT     0X20
#define SDE_DS21Q50_RESF     0x10
#define SDE_DS21Q50_RESE     0X8
#define SDE_DS21Q50_CRCRC    0x4
#define SDE_DS21Q50_FASRC    0x2
#define SDE_DS21Q50_CASRC    0x1*/
/*--------RIR-----------------*/

/*--------SSR-----------------*/
/*#define SDE_DS21Q50_CSC5     0X80
#define SDE_DS21Q50_CSC4     0X40
#define SDE_DS21Q50_CSC3     0X20
#define SDE_DS21Q50_CSC2     0x10
#define SDE_DS21Q50_CSC0     0X8
#define SDE_DS21Q50_FASSA    0x4
#define SDE_DS21Q50_CASSA    0x2
#define SDE_DS21Q50_CRC4SA   0x1*/
/*--------SSR-----------------*/

/*#define SDE_DS21Q50_FRCL     0X80
#define SDE_DS21Q50_RPE      0X40
#define SDE_DS21Q50_RPS      0X20
#define SDE_DS21Q50_RHALF    0x10
#define SDE_DS21Q50_RNE      0X8
#define SDE_DS21Q50_THALF    0x4
#define SDE_DS21Q50_TNF      0x2
#define SDE_DS21Q50_TMEND    0x1


#define REG_SR1           1
#define REG_SR2           2
#define REG_RIR           3
#define REG_HSR           4
#define REG_SSR           5*/

typedef struct{
	UCHAR VCR1;
	UCHAR VCR2;
	UCHAR CRCCR1;
	UCHAR CRCCR2;
	UCHAR EBCR1;
	UCHAR EBCR2;
	UCHAR FASCR1;
	UCHAR FASCR2;
	UCHAR RIR;
	UCHAR SSR;
	UCHAR SR1;
	UCHAR SR2;	
	UCHAR Reserved[3];
	UCHAR IDR;
	UCHAR RCR;
	UCHAR TCR;
	UCHAR CCR1;
	UCHAR CCR2;
	UCHAR CCR3;
	UCHAR CCR4;
	UCHAR CCR5;
	UCHAR LICR;

	UCHAR IMR1;
	UCHAR IMR2;
	UCHAR OUTAC;
	UCHAR OUTBC;
	UCHAR IBOR;
	UCHAR SCICR;
	UCHAR TEST2;
	UCHAR TEST3;
	UCHAR TAF;
	UCHAR TNAF;
	UCHAR TDS0M;
	UCHAR TIDR;
	UCHAR TIR1;
	UCHAR TIR2;
	UCHAR TIR3;
	UCHAR TIR4;
	UCHAR RAF;
	UCHAR RNAF;
	UCHAR RDS0M;
	UCHAR PCLB1;
	UCHAR PCLB2;
	UCHAR PCLB3;
	UCHAR PCLB4;
	UCHAR TEST1;
}DS21Q50Reg;

typedef struct{
	UCHAR *BaseAddr;
	int SyncIF;
	ULONG Timer;
        ULONG RPSlipCnt;
        ULONG RNSlipCnt;
}DS21Q50CfgStruct;

typedef struct{
	/*int Timer;
	int RSlip;*/
	int RPSlip;
	int RNSlip;
	/*int TPSlip;
	int TNSlip;
	int RPSlipCnt;
	int RNSlipCnt;
	int TPSlipCnt;
	int TNSlipCnt;*/
	int RLOS;
	int RCL;
}DS21Q50WarningStruct;

#define WARNINGTIMECNT   50
#define SLIP_TH          5 

static UCHAR SRead(UCHAR *pReg);
UCHAR *DS21Q50BspInit(int DEV, char *FreeMemPtr, DS21Q50CfgStruct *cfg);
#endif