upmtab.c

这是单板上DPRAM的驱动程序

/* @(#) pSOSystem/PPC V221 */
/***********************************************************************/
/*                                                                     */
/*   MODULE:  bsps/BRP8xx/src/upmtab.c                                 */
/*   DATE:    99/10/23                                                 */
/*   AUTHOR:  chenjun                                                  */
/*   PURPOSE: UPMA Dynamic Initialization Module                       */
/*---------------------------------------------------------------------*/
/*           Copyright 1999 - 2000, ZHONGXING TELECOM CO.,LTD.         */
/*                      ALL RIGHTS RESERVED                            */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*                                                                     */
/***********************************************************************/
#include "bsp.h"
#include <bspfuncs.h>
#include "board.h"
#include "bspcomm.h"

/************************************************************************/
/* Function Prototypes                                               */
/************************************************************************/
#define SDRAM_DELAY 80000
#define MAX_ENTRIES 0x40
#define BD_DRAM_MAMR_VALUE  0x18862111 /* PTA=18,PTAE=1,AMA=000,GPL0=A11 */

/************************************************************************/
/*      UPM contents table for 860FUC memory configuration              */
/*          UPMA Initialization for -15 SDRAMs @ 50Mhz                  */
/************************************************************************/
const ULONG UpmTable[MAX_ENTRIES]=
	{
/* Single Read */
0xf03fc24,0xffffc04,0xacfc04,0xffffc00,
0xff33c04,0xfffffc67,0xfffffc67,0xfffffc67,
/* Burst Read */
0xf03fc24,0xffffc04,0xfcfc04,0xfffc08,
0xfffc08,0xfffc08,0xff33c00,0x1ffffc67,
0xfffffc67,0xffffffff,0xffffffff,0xffffffff,
0xffffffff,0xffffffff,0xffffffff,0xffffffff,
/* Single Write */
0xf03fc24,0xffffc00,0xac3c04,0xffffc04,
0xff33c04,0xfffffc47,0xfffffc67,0xffffffff,
/* Burst Write */
0xf03fc24,0xffffc00,0xfc3c08,0xfffc08,
0xfffc08,0xfffc04,0xff33c04,0xfffffc67,
0xfffffc67,0xffffffff,0xffffffff,0xffffffff,
0xffffffff,0xffffffff,0xffffffff,0xffffffff,
/* Fresh */
0xff0fc24,0xfffffc04,0xfffffc04,0xfffffc04,
0xfffffc27,0xfffffc04,0xfffffc67,0xffffffff,
0xffffffff,0xffffffff,0xffffffff,0xffffffff,
/* Exception */
0xfffffc67,0xffffffff,0xffffffff,0xffffffff,
	/* End oF table indicator */
	}; /* End oF SDRAM -15 table @ 50Mhz */

/************************************************************************/
/*           UPMA Initialization For Power UP initalization   -15@40MHz    */
/************************************************************************/
const ULONG PowerUpTable[MAX_ENTRIES]={
	/*  single read. (offset 0x0 - 0x7 in upm RAM)                          */
        0xffffcc24, 0x0f0ccc04, 0x0fffcc04, 0x00af0c04, 0x00f0cc00,
        0x11ffcc67,
        0xffffffff, 0xffffffff, /* OFFsets 6-7 not used */

	/* burst read. (oFFset 0x8 - 0x17 in upm RAM)                            */
	0xfffffc04, 0x0ff33c04, 0xfffffc04, 0xfffffc84,
	0x0ff0fc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
       0xfffffc04, 0xfffffc84, 0xfffffc34, 0x0fa00c34,
	0xfffffc04, 0xfffffc67, 0xffffffff, 0xffffffff,

	/* single write. (oFFset 0x18 - 0x1F  in upm RAM)				*/
	0xffffec24, 0x0f0cec04, 0x0fffec04, 0x00a32c00, 0x00f0ec04,
	0x10ffec67, 

	/* OFF 1E-1F !used */
	0xffffffff, 0xffffffff,

	/*  burst write. (oFFset 0x20 -  0x2F in upm RAM) */
	0xffffec24, 0x0f0ccc04, 0x0fffcc04, 0x00f30c00, 0x00ffcc00,
	0x00ffcc00, 0x00ffcc00, 0x00ffcc04, 0x11ffcc67, 
	0xffffffff, 
	/* OFFsets 2b-2F not used */
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 
	0xffffffff, 0xffffffff,

	/*  ReFresh. (oFFset 0x30 - 0x3B in upm RAM) */
	0xffffec04, 0x0ffc2c04, 0xffffec04, 0xffffec04, 0xffffec67,
	/*  OFFsets 37-3b not used */
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff,

	/*  Exception. (oFFset 0x3c - 0x3F in upm RAM) */
	0xffffec27, 0xffffffff, 0xffffffff, 0xffffffff
	};


/***********************************************************************/
/*     InitUpma: Initializes the UPMA registers to the specified CPU   */
/*               speed and Dram attributes.                            */
/*                                                                     */
/*     RETURNS: None                                                   */
/*                                                                     */
/***********************************************************************/
void InitUpma(void)
{
    ULONG ii;
    PDA    *IOMemMap;

    /* Get the pointer to Internal Memory Map */
    IOMemMap = (PDA *)(GetIMMR() & IO_MAP_MASK);

    for(ii=0;ii<MAX_ENTRIES;ii++)
       {	
        /* Write to the UPMA register */		
        IOMemMap->memc_mdr = UpmTable[ii];
        IOMemMap->memc_mcr = 0x00000000 + ii;      /* Command: OP=Write, UPMA, MAD=0 */
	}
}

/***********************************************************************/
/*     InitMemController: Initializes the refresh logic of the memory  */
/*                        controller.                                  */
/*                                                                     */
/*     RETURNS: None                                                   */
/*                                                                     */
/***********************************************************************/
void InitMemController(void)
{
    volatile delay_cnt;

/*-------------------------------------------------------------------*/
/* Wait at least 200 usec for SDRAM to stabilize, this magic number   */
/* obtained from the init code.                                      */
/*-------------------------------------------------------------------*/
    delay_cnt = 0;
    while (delay_cnt++ < SDRAM_DELAY); 
    delay_cnt = 0; 
    while (delay_cnt++ < SDRAM_DELAY);

/*-------------------------------------------------------------------*/
/* Need at least 10 SDRAM accesses to stabilize.                      */
/* Perform a test write and read from the DRAM to make sure it has   */
/* stabilized.                                                       */
/*-------------------------------------------------------------------*/
    for (delay_cnt = 0; delay_cnt < 10; delay_cnt ++) {
        ULONG TmpVar= REG32(BD_DRAM_BASE_ADDR + 0x1000 + delay_cnt);
	 REG32(BD_DRAM_BASE_ADDR + 0x1000 + delay_cnt) = TmpVar;
        }
}

void InitSDRAM(void)
{

volatile delay_cnt;
ULONG ii, Value;
PDA   *IOMemMap;
/*---------------------------------------------------------------------*/
/* Get the pointer to Internal Memory Map                              */
/*---------------------------------------------------------------------*/
IOMemMap = (PDA *)(GetIMMR() & IO_MAP_MASK);

IOMemMap->memc_mptpr = 0x0400;     /* 16 */ /* ----cj */
IOMemMap->memc_mamr = 0x18062111;  /* for init sdram option */

/*-------------------------------------------------------------------*/
/* Wait at least 200 usec for SDRAM to stabilize, this magic number   */
/* obtained from the init code.                                      */
/*-------------------------------------------------------------------*/
delay_cnt = 0; 
while (delay_cnt++ < SDRAM_DELAY);
delay_cnt = 0; 
while (delay_cnt++ < SDRAM_DELAY); 

for(ii=8;ii<0x18;ii++){
	/* Write to the UPMA register */
	IOMemMap->memc_mdr = PowerUpTable[ii];
	IOMemMap->memc_mcr = 0x00000000 + ii;      /* Command: OP=Write, UPMA, MAD=0 */
	}

IOMemMap->memc_mdr = 0xffffffff;  /* Mode set  latency=2, burst=4 sequential */
IOMemMap->memc_mar = 0x02000088;
IOMemMap->memc_mcr = 0x80004a08;

/*-------------------------------------------------------------------*/
/* Wait at least 200 usec for SDRAM to stabilize, this magic number   */
/* obtained from the init code.                                      */
/*-------------------------------------------------------------------*/
delay_cnt = 0;
while (delay_cnt++ < SDRAM_DELAY);
delay_cnt = 0;
while (delay_cnt++ < SDRAM_DELAY);

}

void HdwInitDRAM(void)
{
ULONG s_pll_val;
PDA   *IOMemMap;
volatile delay_cnt;
/* ----cj */
    S_PortBPinAssgmntReg&=0xFFFFFCFF;  /* enable ALM & RUN LED */
    S_PortBDataDirReg|=0x300;
    S_PortBOpenDrainReg&=0x0FCFF;
    S_PortBDataReg&=~0x300;

resetSWT();
/*---------------------------------------------------------------------*/
/* Get the pointer to Internal Memory Map                              */
/*---------------------------------------------------------------------*/
IOMemMap = (PDA *)(GetIMMR() & IO_MAP_MASK);

/*---------------------------------------------------------------------*/
/* Get the normalized CPU speed. To do that, caculate the value for    */
/* the PLL multiplier factor according to the disired speed, then      */
/* caculate the normalized CPU speed according to the PLL multiplier   */
/* factor.  The equation used is                                       */
/*      Input clock (Mhz) X (Multplier +1) = Cpu speed (Mhz)           */
/*                                                                     */
/* The input clock is normally either 4Mhz or 32.768KHz. The factor    */
/* is stored in the bit 0 to bit 11  PLL control register.             */
/*---------------------------------------------------------------------*/
/* ----cj <arch.h>*/
s_pll_val = ((BD_CPU_SPEED*1000000)/BD_INPUT_CLOCK) -1;
S_PLL_ControlReg = (s_pll_val << 20);
delay_cnt = 0;
while (delay_cnt++ < SDRAM_DELAY);

InitSDRAM();  /* power up */

delay_cnt = 0;
while (delay_cnt++ < SDRAM_DELAY); 

/*---------------------------------------------------------------------*/
/* Initialize the UPMA registers with the appropriate table. The       */
/* selection of the table based on the CPU speed, SDRAM speed and the   */
/* type of SDRAM installed on the board.                                */
/*---------------------------------------------------------------------*/
/* ----cj <arch.h>*/
InitUpma();
IOMemMap->memc_mamr = BD_DRAM_MAMR_VALUE;/* PTA=A0, AMX=000, DSA=00,GL0=A11,LOOP=1 */
IOMemMap->memc_or2 = OR2_VAL;   /* 4M and Burst inhibit for intalization */
IOMemMap->memc_br2 = BR2_VAL;   /* Base address is 0, select upma as controller */
IOMemMap->memc_mdr = 0xffffffff;
IOMemMap->memc_mar = 0x00000000;

/*---------------------------------------------------------------------*/
/* Initialize the Memory Controller registers, MPTPR, Chip Select 4 for*/
/* SDRAM                                                               */
/*                                                                     */
/* NOTE: The refresh rate in MBMR reg is set according to the lowest   */
/*       clock rate (16.67MHz) to allow proper operation for all target*/
/*       clock frequencies.                                            */
/*---------------------------------------------------------------------*/
InitMemController();

{
    int i;
    char *testram=(char *)BD_DRAM_BASE_ADDR;
	resetSWT();
    for(i=0;i<BD_DRAM_SIZE;i+=0x2714)testram[i]=(i&0xff);
    for(i=0;i<BD_DRAM_SIZE;i+=0x2714)if(testram[i]!=(i&0xff))break;
	S_PortBDataReg|=0x300;
    if(i<BD_DRAM_SIZE)
    {
	    S_PortBDataReg&=~0x200;
        while(1);
    }
}
    
resetSWT();
}