arch.h

这是单板上DPRAM的驱动程序

/* @(#) pSOSystem/PPC V221 */
/***********************************************************************/
/*                                                                     */
/*   MODULE:  mpc8xx/ecom/src/arch.h                                   */
/*   DATE:    99/10/22                                                 */
/*   AUTHOR:  Dong Aiping                                              */
/*   PURPOSE:                                                          */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*                                                                     */
/*           Copyright 1999 - 2000, ZHONGXING TELECOM CO.,LTD.         */
/*                      ALL RIGHTS RESERVED                            */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*                                                                     */
/*  This file include functions about the MPC860                       */
/*                                                                     */
/***********************************************************************/

#ifndef _ARCH_H_
#define _ARCH_H_

/* if you make another bsp, next items should be defined forcely */
#define BD_QMC_CHAN_NUM1 32
#define BD_QMC_CHAN_NUM2 16

# define MAX_UNCACHED_BUFFER_LEN (1024*256)
#define SDN_MAX         80
#define BD_INPUT_CLOCK  BD_4MHZ_INPUT
#define BD_CPU_SPEED    64
#define S_REGISTER_BASE 0x80000000

/* BRn @ 16-8,    ORn @ 16-10 */

/* Chip select 0 for BOOT ROM */
# define CS0_ATTR ( PAGE_VALID | PAGE_CACHE_ENABLE | PAGE_SIZE_4K |  \
           PAGE_HIT_BOTH | PAGE_UNCHANGE | PAGE_EN_PPC | PAGE_PP_EEWW)
#define CS0_BASE 0xfff00000 
#define CS0_SIZE 0x80000
#define BR0_VAL  ( CS0_BASE+0X0501) /* 16-8 */
#define OR0_VAL  (0xFFFFFFFF-(CS0_SIZE-1)+0x0926) /* 16-10 */

/* Chip select 1 for FLASH */
# define CS1_ATTR ( PAGE_VALID | PAGE_CACHE_DISABLE | PAGE_SIZE_4K |  \
                   PAGE_HIT_BOTH|PAGE_CHANGE|PAGE_EN_PPC|PAGE_PP_EEWW)
#define CS1_BASE 0x02800000 
#define CS1_SIZE 0x200000  
#define BR1_VAL  ( CS1_BASE+0x0801)
#define OR1_VAL  (0xFFFFFFFF-(CS1_SIZE-1)+0x0926)

/* Chip select 2 for 16M SDRAM */
# define CS2_ATTR ( PAGE_VALID | PAGE_CACHE_ENABLE | PAGE_SIZE_4K | \
                   PAGE_HIT_BOTH|PAGE_CHANGE|PAGE_EN_PPC|PAGE_PP_EEWW)
#define CS2_BASE 0x00000000 
#define CS2_SIZE 0x1000000 
#define BR2_VAL  ( CS2_BASE+0x0081)
#define OR2_VAL  (0xFFFFFFFF-(CS2_SIZE-1)+0x0800)

/*  Chip select 3 for MT8986(2)  */
# define CS3_ATTR ( PAGE_VALID | PAGE_CACHE_DISABLE | PAGE_SIZE_4K | \
             PAGE_HIT_BOTH | PAGE_CHANGE | PAGE_EN_PPC | PAGE_PP_EEWW )
#define CS3_BASE 0x50008000
#define CS3_SIZE 0x8000 
#define BR3_VAL  ( CS3_BASE+0x401)
#define OR3_VAL  (0xFFFFFFFF-(CS3_SIZE-1)+0x90E)
        /* CSNT=1;ACS=00;BI=1 | SCY=0000 | SETA=1;TRLX=1;ETHR=1;- */


/* Chip select 4 for UP DPRAM -No Parity */
# define CS4_ATTR ( PAGE_VALID | PAGE_CACHE_DISABLE | PAGE_SIZE_4K | \
               PAGE_HIT_BOTH | PAGE_CHANGE | PAGE_EN_PPC | PAGE_PP_EEWW)
#define CS4_BASE 0x30000000
#define CS4_SIZE 0x8000 
#define BR4_VAL  ( CS4_BASE+0x0A01)
#define OR4_VAL  (0xFFFFFFFF-(CS4_SIZE-1)+0x95E)
        /* CSNT=1;ACS=00;BI=1 | SCY=0101 | SETA=1;TRLX=1;ETHR=1;- */

/* Chip select 5 for DOWN DPRAM -No Parity */
# define CS5_ATTR ( PAGE_VALID | PAGE_CACHE_DISABLE | PAGE_SIZE_4K |  \
          PAGE_HIT_BOTH | PAGE_CHANGE | PAGE_EN_PPC | PAGE_PP_EEWW )
#define CS5_BASE 0x30008000
#define CS5_SIZE 0x8000 
#define BR5_VAL  ( CS5_BASE+0x0A01)
#define OR5_VAL  (0xFFFFFFFF-(CS5_SIZE-1)+0x95E)
        /* CSNT=1;ACS=00;BI=1 | SCY=0101 | SETA=1;TRLX=1;ETHR=1;- */

/*  Chip select 6 for MT8986  */
# define CS6_ATTR ( PAGE_VALID | PAGE_CACHE_DISABLE | PAGE_SIZE_4K | \
             PAGE_HIT_BOTH | PAGE_CHANGE | PAGE_EN_PPC | PAGE_PP_EEWW )
#define CS6_BASE 0x50000000
#define CS6_SIZE 0x8000 
#define BR6_VAL  ( CS6_BASE+0x401)
#define OR6_VAL  (0xFFFFFFFF-(CS6_SIZE-1)+0x90E)
        /* CSNT=1;ACS=00;BI=1 | SCY=0000 | SETA=1;TRLX=1;ETHR=1;- */

/* Invalid Page */
# define CS7_ATTR ( PAGE_INVALID | PAGE_CACHE_DISABLE | PAGE_SIZE_4K | \
             PAGE_HIT_BOTH | PAGE_CHANGE | PAGE_EN_PPC | PAGE_PP_EEWW )
#define CS7_BASE 0x70000000
#define CS7_SIZE 0x8000 
#define BR7_VAL  ( CS7_BASE+0x400)
#define OR7_VAL  (0xFFFFFFFF-(CS7_SIZE-1)+0x926)

#define BD_DRAM_BASE_ADDR CS2_BASE
#define BD_DRAM_SIZE      CS2_SIZE

#endif /* _ARCH_H_ */