📄 cstartx.asm
字号:
;*****************************************************************************
;*
;* MODULE : cstartx.asm
;*
;* DESCRIPTION : C startup code for extended C166 architecture CPU's
;* (e.g. C161x, C163, C164xx, C165, C167xx, ST10-262).
;*
;* - Processor initialization.
;* - Initialization of static variables in internal or external
;* ram is done in '_c_init.asm'.
;* - Call the user program: main().
;* - On exit cpu is set in idle mode.
;*
;* COPYRIGHTS : 1998 TASKING, Inc.
;*
;*****************************************************************************
$CHECKCPU16
$NOMOD166 ; disable the internal set of SAB 80C166 SFRs
$STDNAMES(reg167.def) ; use extended set of SFR's (BUSCON0 etc.)
$include(head.asm)
$include(_c_init.asm) ; initialization of static variables in internal or external ram.
NAME CSTART ; module name.
PUBLIC RBANK
@IF( @EQS(@MODEL,"LARGE") | @EQS(@MODEL,"SMALL") )
@IF( @DEFINED( @CALLEINIT))
EXTERN @CALLEINIT:FAR ; optional call before EINIT
@ENDI
@IF( @DEFINED( @CALLINIT))
EXTERN @CALLINIT:FAR ; optional call before _main
@ENDI
EXTERN _main:FAR ; start label user program.
@ELSE
@IF( @DEFINED( @CALLEINIT))
EXTERN @CALLEINIT:NEAR ; optional call before EINIT
@ENDI
@IF( @DEFINED( @CALLINIT))
EXTERN @CALLINIT:NEAR ; optional call before _main
@ENDI
EXTERN _main:NEAR ; start label user program.
@ENDI
PUBLIC __IDLE ; cstart end
PUBLIC __EXIT ; address to jump to on 'exit()'.
@IF( @EX_AB )
@IF( @EQS(@MODEL,"LARGE") | @EQS(@MODEL,"SMALL") )
EXTERN _exit:FAR ; exit()
@ELSE
EXTERN _exit:NEAR ; exit()
@ENDI
@ENDI
@IF( @EQS( @MODEL, "SMALL") | @EQS( @MODEL, "LARGE") )
EXTERN __C_INIT:FAR
@ELSE
EXTERN __C_INIT:NEAR
@ENDI
; Value definitions for System Configuration Register : SYSCON
; XBUS Peripheral Share Mode Control (XPER-SHARE) bit. SYSCON.0
@IF( ! @DEFINED( __XPER_SHARE ) )
@SET(__XPER_SHARE, 0) ; 0 = Disable external accesses to XBUS peripherals
@ENDI ; 1 = XBUS peripherals accessible via
; external bus during hold mode
; Visible Mode Control (VISIBLE) bit. SYSCON.1
@IF( ! @DEFINED( __VISIBLE ) )
@SET(__VISIBLE, 0) ; 0 = Accesses to XBUS peripherals internally
@ENDI ; 1 = XBUS peripherals accessible visible on
; external pins
; XBUS Peripheral (XPEN) Enable bit. SYSCON.2
@IF( ! @DEFINED( __XPEN ) )
@SET(__XPEN, 0) ; 0 = On-chip X-Peripherals accesses
@ENDI ; are done internally
; 1 = On-chip X-Peripherals Enable
; Bidirectional Reset (BDRSTEN) Enable bit. SYSCON.3
@IF( ! @DEFINED( __BDRSTEN ) )
@SET(__BDRSTEN, 0) ; 0 = Pin RSTIN is input only
@ENDI ; 1 = Pin RSTIN pulled low during internal
; reset after software or WDT reset
; Oscillator Watchdog (OWDDIS) Disable bit. SYSCON.4
@IF( ! @DEFINED( __OWDDIS ) )
@SET(__OWDDIS, 1) ; 0 = Enable on-chip oscillator watchdog
@ENDI ; 1 = Disable on-chip oscillator watchdog
; Chip Selected Configuration Control (CSCFG) bit. SYSCON.6
@IF( ! @DEFINED( __CSCFG ) )
@SET(__CSCFG, 0) ; 0 = Latched CS mode
@ENDI ; 1 = Unlatched CS mode
; Write Configuration Mode Control Bit (CLKOUT) Enable bit. SYSCON.7
@IF( ! @DEFINED( __WRCFG ) )
@SET(__WRCFG, 0) ; 0 = Normal operation of WR# abd BHE# (Reset)
@ENDI ; 1 = WR# acts as WRL#, BHE# acts as WRH#
; System Clock Output (CLKOUT) Enable bit. SYSCON.8
@IF( ! @DEFINED( __CLKEN ) )
@SET(__CLKEN, 0) ; 0 = Disabled (Reset value)
@ENDI ; 1 = Enabled
; Byte High Enable (BHE#) pin control bit. SYSCON.9
@IF( ! @DEFINED( __BYTDIS ) )
@SET(__BYTDIS, 0) ; 0 = Enabled (Reset value)
@ENDI ; 1 = Disabled
; Internal ROM Access (ROMEN) Enable bit. SYSCON.10
; Reset value determined by EA pin
@IF( ! @DEFINED( __ROMEN ) )
@SET(__ROMEN, 0) ; 0 = Disable Internal ROM
@ENDI ; 1 = Enable Internal ROM
; Segmentation Disable control bit. SYSCON.11
@IF( ! @DEFINED( __SGTDIS ) )
@IF( @EQS( @MODEL, "TINY" ) & NOT (@EVA) )
@SET(__SGTDIS, 1) ; 1 = Disable segmented memory mode
; for TINY model and NOT EVA
@ELSE
@SET(__SGTDIS, 0) ; 0 = Reset value is segmentation enabled
@ENDI
@ENDI
; ROM Segment Mapping control bit. SYSCON.12
@IF( ! @DEFINED( __ROMS1 ) )
@SET(__ROMS1, 0) ; 0 = Map internal ROM to segment 0 (Reset)
@ENDI ; 1 = Map internal ROM to segment 1
; Stack Size selection of between 32 and 512 words. SYSCON[15..13]
@IF( ! @DEFINED( __STKSZ ) ) ; System stack size
@SET(__STKSZ, 0) ; 0 = 256 words (Reset value)
@ENDI ; 1 = 128 words
; 2 = 64 words
; 3 = 32 words
; 4 = 512 words
; 7 = No wrapping
; Process SYSCON low byte and high byte values.
SYSC_L EQU ((@__WRCFG<<7) | (@__CSCFG<<6) | (@__OWDDIS<<4) | (@__BDRSTEN<<3) | (@__XPEN<<2) | (@__VISIBLE<<1) | @__XPER_SHARE)
SYSC_H EQU ((@__STKSZ<<5) | (@__ROMS1<<4) | (@__SGTDIS<<3) | (@__ROMEN<<2) | (@__BYTDIS<<1) | @__CLKEN)
SYSC_M_L EQU 0DFH ; Mask low byte SYSCON.
SYSC_M_H EQU 0FFH ; Mask high byte SYSCON.
; Value definitions for System Configuration Register : SYSCON2
; SYSCON Release Function (SYSRLS) field. SYSCON2[0..3]
; Unlock sequence field after EINIT
; Power Down Control (PDCON) field. SYSCON2[4..5]
@IF( ! @DEFINED( __PDCON ) )
@SET(__PDCON, 0 ) ; 0 = RTC on, Ports on (Reset)
@ENDI ; 1 = RTC on, Ports off
; 2 = RTC off, Ports on
; 3 = RTC off, Ports off
; RTC Clock Source (RCS) bit. SYSCON2.6
@IF( ! @DEFINED( __RCS ) )
@SET(__RCS, 0 ) ; 0 = Main oscillator
@ENDI ; 1 = Reserved
; SDD Clock Source (SCS) bit. SYSCON2.7
@IF( ! @DEFINED( __SCS ) )
@SET(__SCS, 0 ) ; 0 = Main oscillator
@ENDI ; 1 = Reserved
; Clock State Control (CLKCON) field. SYSCON2[8..9]
@IF( ! @DEFINED( __CLKCON ) )
@SET(__CLKCON, 0 ) ; 0 = Run on configured basic frequency
@ENDI ; 1 = Run on slow down frequency, PLL ON
; 2 = Run on slow down frequency, PLL OFF
; Reload Counter Value for Slowdown Divider (CLKREL) field. SYSCON2[10..14]
@IF( ! @DEFINED( __CLKREL ) )
@SET(__CLKREL, 0 ) ; Reload value
@ENDI
; Clock Signal Status (CLKLOCK) bit is read only. SYSCON2.15
; Process SYSCON2 low byte and high byte values.
SYSC2_L EQU ((@__SCS<<7) | (@__RCS<<6) | ((@__PDCON&0003h)<<4))
SYSC2_H EQU (((@__CLKREL&001fh)<<2) | (@__CLKCON&0003h))
SYSC2_M_L EQU 0F0H ; Mask low byte SYSCON2.
SYSC2_M_H EQU 07FH ; Mask high byte SYSCON2.
; Value definitions for System Configuration Register : SYSCON3
; Analog/Digital Converter (ADCDIS) enable bit. SYSCON3.0
@IF( ! @DEFINED( __ADCDIS ) )
@SET(__ADCDIS, 0) ; 0 = Disable ADC convertor
@ENDI ; 1 = Enable ADC convertor
; USART ASC0 (ASC0DIS) enable bit. SYSCON3.1
@IF( ! @DEFINED( __ASC0DIS ) )
@SET(__ASC0DIS, 0) ; 0 = Disable USART ASC0
@ENDI ; 1 = Enable USART ASC0
; Synchronous Serial Channel SSC (SSCDIS) enable bit. SYSCON3.2
@IF( ! @DEFINED( __SSCDIS ) )
@SET(__SSCDIS, 0 ) ; 0 = Disable Synchronous Serial Channel SSC
@ENDI ; 1 = Enable Synchronous Serial Channel SSC
; General Purpose Timer Blocks (GPTDIS) enable bit. SYSCON3.3
@IF( ! @DEFINED( __GPTDIS ) )
@IF( ! @DEFINED( __GPT1DIS ) )
@SET(__GPTDIS, 0 ) ; 0 = Disable General Purpose Timer Blocks
; 1 = Enable General Purpose Timer Blocks
@ELSE
@SET(__GPTDIS, @__GPT1DIS)
@ENDI
@ENDI
; General Purpose Timer Block 2 (GPT2DIS) enable bit. SYSCON3.4
@IF( ! @DEFINED( __GPT2DIS ) )
@SET(__GPT2DIS, 0 ) ; 0 = Disable General Purpose Timer Block 2
@ENDI ; 1 = Enable General Purpose Timer Block 2
; On-chip Flash Memory Module (FMDIS) enable bit. SYSCON3.5
@IF( ! @DEFINED( __FMDIS ) )
@SET(__FMDIS, 0 ) ; 0 = Disable on-chip Flash Memory Module
@ENDI ; 1 = Enable on-chip Flash Memory Module
; CAPCOM Unit 1 (CC1DIS) enable bit. SYSCON3.6
@IF( ! @DEFINED( __CC1DIS ) )
@SET(__CC1DIS, 0 ) ; 0 = Disable CAPCOM Unit 1
@ENDI ; 1 = Enable CAPCOM Unit 1
; CAPCOM Unit 2 (CC2DIS) enable bit. SYSCON3.7
@IF( ! @DEFINED( __CC2DIS ) )
@SET(__CC2DIS, 0 ) ; 0 = Disable CAPCOM Unit 2
@ENDI ; 1 = Enable CAPCOM Unit 2
; CAPCOM Unit 6 (CC6DIS) enable bit. SYSCON3.8
@IF( ! @DEFINED( __CC6DIS ) )
@SET(__CC6DIS, 0 ) ; 0 = Disable CAPCOM Unit 6
@ENDI ; 1 = Enable CAPCOM Unit 6
; USART ASC1 (ASC1DIS) enable bit. SYSCON3.10
@IF( ! @DEFINED( __ASC1DIS ) )
@SET(__ASC1DIS, 0) ; 0 = Disable USART ASC1
@ENDI ; 1 = Enable USART ASC1
; On-chip I2C Bus Module (I2CDIS) enable bit. SYSCON3.11
@IF( ! @DEFINED( __I2CDIS ) )
@SET(__I2CDIS, 0 ) ; 0 = Disable On-chip I2C Bus Module
@ENDI ; 1 = Enable On-chip I2C Bus Module
; On-chip CAN Module 1 (CAN1DIS) enable bit. SYSCON3.13
@IF( ! @DEFINED( __CAN1DIS ) )
@SET(__CAN1DIS, 0 ) ; 0 = Disable On-chip CAN Module 1
@ENDI ; 1 = Enable On-chip CAN Module 1
; Peripheral Clock Driver (PCDDIS) enable bit. SYSCON3.15
@IF( ! @DEFINED( __PCDDIS ) )
@SET(__PCDDIS, 0 ) ; 0 = Disable Peripheral Clock Driver
@ENDI ; 1 = Enable Peripheral Clock Driver
; Process SYSCON3 low byte and high byte values.
SYSC3 EQU ((@__PCDDIS<<15) | (@__CAN1DIS<<13) | (@__I2CDIS<<11) | (@__ASC1DIS<<10) | (@__CC6DIS<<8) | (@__CC2DIS<<7) | (@__CC1DIS<<6) |(@__FMDIS<<5) | (@__GPT2DIS<<4) | (@__GPTDIS<<3) |(@__SSCDIS<<2) |(@__ASC0DIS<<1) | @__ADCDIS)
; Value definitions for System Configuration Register : BUSCON0
; Memory Cycle Time is extended by a number of additional State Times.
; in a range from 0 through 15. BUSCON0[3..0]
; Reset value MCTC = 15 additional state times
@IF( ! @DEFINED( __MCTC ) )
@SET(__MCTC, 1) ; 1 = Memory wait states is 1 (MCTC = 0EH).
@ENDI ; 0 = Memory wait states is 0 (MCTC = 0FH).
; The Read/Write Signal Delay is 0.5 or 0 State Times. BUSCON0.4
@IF( ! @DEFINED( __RWDC0 ) )
@SET(__RWDC0, 1) ; 1 = No Delay Time
@ENDI ; 0 = Delay Time (Reset value)
; Memory Tri-state is extended by either 1 or 0 State Times. BUSCON0.5
@IF( ! @DEFINED( __MTTC0 ) )
@SET(__MTTC0, 0) ; 0 = Delay Time (Reset value)
@ENDI ; 1 = No Delay Time
; External bus configurations. BUSCON0[7..6]
; After reset determined by the state
; of the port pins P0L.7 and P0L.6.
; ALE Signal is lengthened by either 1 or 0 State Times. BUSCON0.9
; Do not disable the ALE lengthening option for a multiplexed bus
; configuration. See problem 17 in errata sheet SAB-C167A-LM,ES-AC,1.1
; on page 4/9.
@IF( ! @DEFINED( __ALECTL0 ) )
@IF( @MUXBUS )
@SET(__ALECTL0, 1) ; 1 = Delay (Reset value if EA# pin is high
@ELSE
@SET(__ALECTL0, 0) ; 0 = No Delay (Reset value if EA# pin is high
@ENDI
@ENDI
; Bus Active (BUSACT0) control bit. BUSCON0.10
@IF( ! @DEFINED( __BUSACT0 ) )
@SET(__BUSACT0, 1 ) ; 0 = Disable external bus
@ENDI ; 1 = Enable external bus
; READY# Input Enable control bit. BUSCON0.12
@IF( ! @DEFINED( __RDYEN0 ) )
@SET(__RDYEN0, 0) ; 0 = Disabled (Reset value)
@ENDI ; 1 = Enabled
; Read Chip Select (CSREN0) enable bit. BUSCON0.14
@IF( ! @DEFINED( __CSREN0 ) )
@SET(__CSREN0,0) ; 0 = Chip select independend of read command
@ENDI ; 1 = Chip select for duration of read command
; Write Chip Select (CSWEN0) enable bit. BUSCON0.15
@IF( ! @DEFINED( __CSWEN0 ) )
@SET(__CSWEN0,0) ; 0 = Chip select independend of write command
@ENDI ; 1 = Chip select for duration of write command
; Process BUSCON0 low byte and high byte values
BUSC0_L EQU ((@__MTTC0<<5) | (@__RWDC0<<4) | ((~@__MCTC)&000Fh))
BUSC0_H EQU ((@__CSWEN0<<7) | (@__CSREN0<<6) | (@__RDYEN0<<4) | (@__BUSACT0<<2) | (@__ALECTL0<<1))
BUSC0_M_L EQU 03Fh ; Mask low byte BUSCON0
BUSC0_M_H EQU 0D6h ; Mask high byte BUSCON0
; Value definitions for System Configuration Register : BUSCON1
; Memory Cycle Time is extended by a number of additional State Times.
; in a range from 0 through 15. BUSCON1[3..0]
; Reset value MCTC = 15 additional state times
@IF( ! @DEFINED( __MCTC1 ) )
@SET(__MCTC1, 1) ; 1 = Memory wait states is 1 (MCTC = 0EH).
@ENDI ; 0 = Memory wait states is 0 (MCTC = 0FH).
; The Read/Write Signal Delay is 0.5 or 0 State Times. BUSCON1.4
@IF( ! @DEFINED( __RWDC1 ) )
@SET(__RWDC1, 1) ; 1 = No Delay Time
@ENDI ; 0 = Delay Time (Reset value)
; Memory Tri-state is extended by either 1 or 0 State Times. BUSCON1.5
@IF( ! @DEFINED( __MTTC1 ) )
@SET(__MTTC1, 0) ; 0 = Delay Time (Reset value)
@ENDI ; 1 = No Delay Time
; External bus configurations. BUSCON1[7..6]
@IF( ! @DEFINED( __BTYP1 ) )
@SET(__BTYP1, 1) ; 0 = 8-bit Demultiplexed Bus
@ENDI ; 1 = 8-bit Multiplexed Bus
; 2 = 16-bit Demultiplexed Bus
; 3 = 16-bit Multiplexed Bus
; ALE Signal is lengthened by either 1 or 0 State Times. BUSCON1.9
@IF( ! @DEFINED( __ALECTL1 ) )
@SET(__ALECTL1, 0) ; 0 = No Delay (Reset value if EA# pin is high
@ENDI ; 1 = Delay (Reset value if EA# pin is high
; Bus Active (BUSACT1) control bit. BUSCON1.10
@IF( ! @DEFINED( __BUSACT1 ) )
@SET(__BUSACT1, 1 ) ; 0 = Disable external bus
@ENDI ; 1 = Enable external bus
; READY# Input Enable control bit. BUSCON1.12
@IF( ! @DEFINED( __RDYEN1 ) )
@SET(__RDYEN1, 0) ; 0 = Disabled (Reset value)
@ENDI ; 1 = Enabled
; Read Chip Select (CSREN1) enable bit. BUSCON1.14
@IF( ! @DEFINED( __CSREN1 ) )
@SET(__CSREN1,0) ; 0 = Chip select independend of read command
@ENDI ; 1 = Chip select for duration of read command
; Write Chip Select (CSWEN1) enable bit. BUSCON1.15
@IF( ! @DEFINED( __CSWEN1 ) )
@SET(__CSWEN1,0) ; 0 = Chip select independend of write command
@ENDI ; 1 = Chip select for duration of write command
; Process BUSCON1 low byte and high byte values
BUSC1 EQU ((@__CSWEN1<<15) | (@__CSREN1<<14) | (@__RDYEN1<<12) | (@__BUSACT1<<10) | (@__ALECTL1<<9) | (@__BTYP1<<6) | (@__MTTC1<<5) | (@__RWDC1<<4) | ((~@__MCTC1)&000Fh))
; Value definitions for System Configuration Register : BUSCON2
; Memory Cycle Time is extended by a number of additional State Times.
; in a range from 0 through 15. BUSCON2[3..0]
; Reset value MCTC = 15 additional state times
@IF( ! @DEFINED( __MCTC2 ) )
@SET(__MCTC2, 1) ; 1 = Memory wait states is 1 (MCTC = 0EH).
@ENDI ; 0 = Memory wait states is 0 (MCTC = 0FH).
; The Read/Write Signal Delay is 0.5 or 0 State Times. BUSCON2.4
@IF( ! @DEFINED( __RWDC2 ) )
@SET(__RWDC2, 1) ; 1 = No Delay Time
@ENDI ; 0 = Delay Time (Reset value)
; Memory Tri-state is extended by either 1 or 0 State Times. BUSCON2.5
@IF( ! @DEFINED( __MTTC2 ) )
@SET(__MTTC2, 0) ; 0 = Delay Time (Reset value)
@ENDI ; 1 = No Delay Time
; External bus configurations. BUSCON2[7..6]
@IF( ! @DEFINED( __BTYP2 ) )
@SET(__BTYP2, 1) ; 0 = 8-bit Demultiplexed Bus
@ENDI ; 1 = 8-bit Multiplexed Bus
; 2 = 16-bit Demultiplexed Bus
; 3 = 16-bit Multiplexed Bus
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -