mcexcep.68k

用于motorala 68K系列处理器的小实时多任务操作系统 The OMU Kernel was written to provide a cut-down Unix-like O/S for a

******************************************************************************
*	Mcexcep.68k	Machine code start up and exception tables
******************************************************************************
*

; Mc - machine code assist for 68000 Unix. T.Barnaby 27-4-85
;	This contains the start up routine for OMU.
;	It must be placed at the start of the omu
;	It sets up the system stack before starting the system
;	Also included is the exception processing table bits.
;

******************************************************************************
*	Omu		start-up routine for OMU.
******************************************************************************
*

;       bss is zeroised
;       'main' is called.
;       'Exit' is here, called from panic routine.
;
	.globl   _main, _edata, _end
	.globl   _exit, _errno

* Note user stack is set by exec on program execution and is thus only
* Set here if a non standard system program is used

usrstack: = 0x060000		;set this to one above your workspace area
sysstack: = 0x020000		;System stack

omu:
	move.w	#$2700,sr	;Mask all interupts
	lea usrstack,a7		;initialise user stack.
	move.l a7,usp
	lea sysstack,a7		;initialise system stack
	movea.l #_edata,a0	;points to first location of bss.

clrloop:
	move.l	#00,(a0)+	;Clears bss area
	cmpa.l	#_end,a0
	blt	clrloop

	jsr     _main           ;Main omu entry point

_exit:
	move #0,d7		;Renters Eltec moniter
	trap #15
;
;

*	Error number, should be in BSS !! (might be now !)

	.bss
_errno:	ds.l 1
	.text


******************************************************************************
*	Exception.68k	Exception and Interupt handler dispatcher, entry points
******************************************************************************
*
*		All of the 68000 exception vectors are set to point
*	into the dispatch table. If the dispatch table is less than
*	the 256	entries required to accomplish this then all vectors
*	above will be set to point to the last entry in the dispatch
*	table.
*		The dispatch table consisits of a sequence of BSR.W
*	instructions which will place on the stack their address in
*	the dispatch table +4, and the jump to the appropriate wrapper
*	for this exception.
*	Note these wrappers must be within +- 32K bytes of the BSR.W.


******************************************************************************
* Interrupt vector dispatch table
* One entry per interrupt vector location
******************************************************************************
*

	.text
	.globl  _dispatc, _wrapper

_dispatc:
	bsr.w	lfault		; 0	Reset: Initial SSP
	bsr.w	lfault		; 1	Reset: Initial PC
	bsr.w	lfault		; 2	Bus Error
	bsr.w	lfault		; 3	Address Error
	bsr.w	lfault		; 4	Illegal Instruction
	bsr.w	lfault		; 5	Zero Divide
	bsr.w	lfault		; 6	CHK Instruction
	bsr.w	lfault		; 7	TRAPV Instruction
	bsr.w	lfault		; 8	Privilege Violation
	bsr.w	lfault		; 9	Trace
	bsr.w	lfault		; 10	Line 1010 Emulator
	bsr.w	lfault		; 11	Line 1111 Emulator
	bsr.w	lfault		; 12	(Unassigned, reserved)
	bsr.w	lfault		; 13	(Unassigned, reserved)
	bsr.w	lfault		; 14	(Unassigned, reserved)
	bsr.w	lfault		; 15	(Unassigned, reserved)
	bsr.w	lfault		; 16	(Unassigned, reserved)
	bsr.w	lfault		; 17	(Unassigned, reserved)
	bsr.w	lfault		; 18	(Unassigned, reserved)
	bsr.w	lfault		; 19	(Unassigned, reserved)
	bsr.w	lfault		; 20	(Unassigned, reserved)
	bsr.w	lfault		; 21	(Unassigned, reserved)
	bsr.w	lfault		; 22	(Unassigned, reserved)
	bsr.w	lfault		; 23	(Unassigned, reserved)
	bsr.w	lfault		; 24	Spurious Interrupt (instrument bus)
	bsr.w	lfault		; 25	Level 1 Interrupt Autovector
	bsr.w	inttick		; 26	Level 2 Interrupt Autovector
	bsr.w	lfault		; 27	Level 3 Interrupt Autovector
	bsr.w	lfault		; 28	Level 4 Interrupt Autovector
	bsr.w	lfault		; 29	Level 5 Interrupt Autovector
	bsr.w	lfault		; 30	Level 6 Interrupt Autovector
	bsr.w	lfault		; 31	Level 7 Interrupt Autovector
	bsr.w	lsys		; 32	TRAP Instruction Vector 0 system call
	bsr.w	lpswtch		; 33	TRAP Instruction Vector 1 process swtch
	bsr.w	lsuper		; 34	TRAP Instruction Vector 2 to super state
	bsr.w	lfault		; 35	TRAP Instruction Vector 3
	bsr.w	lfault		; 36	TRAP Instruction Vector 4
	bsr.w	lfault		; 37	TRAP Instruction Vector 5
	bsr.w	lfault		; 38	TRAP Instruction Vector 6
	bsr.w	lfault		; 39	TRAP Instruction Vector 7
	bsr.w	lfault		; 40	TRAP Instruction Vector 8
	bsr.w	lfault		; 41	TRAP Instruction Vector 9
	bsr.w	lfault		; 42	TRAP Instruction Vector 10
	bsr.w	lfault		; 43	TRAP Instruction Vector 11
	bsr.w	lfault		; 44	TRAP Instruction Vector 12
	bsr.w	lfault		; 45	TRAP Instruction Vector 13
	bsr.w	lfault		; 46	TRAP Instruction Vector 14
	bsr.w	lfault		; 47	TRAP Instruction Vector 15
	bsr.w	intacia		; 48	(Unassigned, reserved) acia interupt
	bsr.w	lfault		; 49	(Unassigned, reserved)
	bsr.w	lfault		; 50	(Unassigned, reserved)
	bsr.w	lfault		; 51	(Unassigned, reserved)
	bsr.w	lfault		; 52	(Unassigned, reserved)
	bsr.w	lfault		; 53	(Unassigned, reserved)
	bsr.w	lfault		; 54	(Unassigned, reserved)
	bsr.w	lfault		; 55	(Unassigned, reserved)
	bsr.w	lfault		; 56	(Unassigned, reserved)
	bsr.w	lfault		; 57	(Unassigned, reserved)
	bsr.w	lfault		; 58	(Unassigned, reserved)
	bsr.w	lfault		; 59	(Unassigned, reserved)
	bsr.w	lfault		; 60	(Unassigned, reserved)
	bsr.w	lfault		; 61	(Unassigned, reserved)
	bsr.w	lfault		; 62	(Unassigned, reserved)
	bsr.w	lfault		; 63	(Unassigned, reserved)


******************************************************************************
*	Lfault	Fault wrapper,	Calls C routine trap() with exception
*				number as argument
******************************************************************************

	.globl	_trap

*	Naughty saves d0 in global varible fsvae plenty of hazards here
*	Left until somting can be done about it
	.bss
fsave:	ds.l 1
	.text

lfault:
	move.l	d0,fsave	;Save d0
	subi.l	#_dispatc+4,(a7);Gets offset into dispatch table
	lsr.w	2(a7)		;Divides number by 4 to get trap number
	lsr.w	2(a7)
	move.l	(a7),d0
	move.l	#_trap,(a7)	;Saves function address on stack
	jsr	_wrapper	;Jumps to common wrapper
	addq.l	#4,a7
	move.l	fsave,d0	;Recover d0
	rte


******************************************************************************
*	Lsys	system trap call,	Jumps to system call wrapper
******************************************************************************

	.globl	_sys

lsys:
	move.l	#_sys,(a7)	;Saves function address over dispatch address
	jsr	_wrapper	;Jump to system wrapper
	addq.l	#4,a7		;Recover stack
	rte

******************************************************************************
*	Lswap	system Concurent swap call,	Switches to new process
******************************************************************************

	.globl	_pswtch

lpswtch:
	move.l	#_pswtch,(a7)	;Saves function address over dispatch address
	jsr	_wrapper	;Jump to system wrapper
	addq.l	#4,a7		;Recover stack
	rte

********************************************************************************
*	Lsuper	Sets super state
********************************************************************************

lsuper:
	addq.l	#4,a7		;Ignore dispatch address
	ori.w	#0x2000,(a7)	;Sets super bit in status word on stack
	rte

******************************************************************************
*	Intacia		Acia interupt	Jumps to ACIA interupt address
*			in tty handler
******************************************************************************

	.globl	_i_acia

intacia:
	addq.l #4,a7		;Remove dispatch table address information */
	movem.l d0-a6,-(a7)
	jsr _i_acia
	movem.l (a7)+,d0-a6
	rte


******************************************************************************
*	Inttick		20ms Timmer interupt
******************************************************************************

	.globl	_tick

;Old tick call does not save processor state
inttick:
	addq.l #4,a7
	movem.l d0-a6,-(a7)
	jsr _tick
	movem.l (a7)+,d0-a6
	rte

*	Codata call for reference
*clock:  movl    #_clock,sp@     ; push call address
*	clrw    sp@-            ; device number
*	jmp     call            ; jump to common interrupt handler


******************************************************************************
*	Sets CPU status ( Led reads 7, 20ms tick on)
******************************************************************************
*

STATUSLED: = 0xFA0100

	.globl	_s_init;

_s_init:
	move.w #$071B,STATUSLED
	rts