tc.inc

嵌入式系统开发用源代码 包含At91C arm芯片相关各种例程 包括整数性能测试,浮点测试,硬件驱动等

;-----------------------------------------------------------------------------
;-      ATMEL Microcontroller Software Support  -   ROUSSET -
;-----------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File Name            : tc.inc
;- Object               : Timer Counter Definition File.
;- Translator           : ARM Software Development Toolkit V2.11a
;-
;- 1.0 19/08/97 JCZ     : Creation
;- 1.1 16/06/98 JCZ     : Update register names same as header file
;- 2.0 21/10/98 JCZ     : Clean up.
;-----------------------------------------------------------------------------

;------------------------
; Timer Counter Structure
;------------------------

                ^       0
TC_CCR          #       4       ; Channel Control Register
TC_CMR          #       4       ; Channel Mode Register
                #       4
                #       4
TC_CV           #       4       ; Counter Value
TC_RA           #       4       ; Register A
TC_RB           #       4       ; Register B
TC_RC           #       4       ; Register C
TC_SR           #       4       ; Status Register
TC_IER          #       4       ; Interrupt Enable Register
TC_IDR          #       4       ; Interrupt Disable Register
TC_IMR          #       4       ; Interrupt Mask Register
                #       4
                #       4
                #       4
                #       4
TC_SIZE         #       0


;------------------------------
; Timer Counter Block Structure
;------------------------------
                ^       0
TC0             #       TC_SIZE
TC1             #       TC_SIZE
TC2             #       TC_SIZE
TC_BCR          #       4
TC_BMR          #       4

;-------------------------------------------------
;- Timer Counter Control Register Bits Definition
;-------------------------------------------------
CLKEN           EQU     (1:SHL:0)
CLKDIS          EQU     (1:SHL:1)
SWTRG           EQU     (1:SHL:2)

;----------------------------------------------
;- Timer Counter Mode Register Bits Definition
;----------------------------------------------

;- Clock Selection
TCCLKS          EQU     (0x7:SHL:0)

;- Clock Inversion
CLKI            EQU     0x08

;- Burst Signal Selection
BURST           EQU     (0x3:SHL:4)

;- Capture Mode : Counter Clock Stopped with RB Loading
LDBSTOP         EQU     0x40

;- Waveform Mode : Counter Clock Stopped with RC Compare
CPCSTOP         EQU     0x40

;- Capture Mode : Counter Clock Disabled with RB Loading
LDBDIS          EQU     0x80

;- Waveform Mode : Counter Clock Disabled with RC Compare
CPCDIS          EQU     0x80

;- Capture Mode : External Trigger Edge Selection
ETRGEDG         EQU     (0x3:SHL:8)

;- Waveform Mode : External Event Edge Selection
EEVTEDG         EQU     (0x3:SHL:8)

;- Capture Mode : TIOA or TIOB External Trigger Selection
ABETRG          EQU     0x400

;- Waveform Mode : External Event Selection
EEVT            EQU     (0x3:SHL:10)

;- Waveform Mode : Enable Trigger on External Event
ENETRG          EQU     0x1000

;- RC Compare Enable Trigger Enable
CPCTRG          EQU     0x4000

;- Mode Selection
WAVE            EQU     0x8000

;- Capture Mode : RA Loading Selection
LDRA            EQU     (0x3:SHL:16)

;- Waveform Mode : RA Compare Effect on TIOA
ACPA            EQU     (0x3:SHL:16)

;- Capture Mode : RB Loading Selection
LDRB            EQU     (0x3:SHL:18)

;- Waveform Mode : RC Compare Effect on TIOA
ACPC            EQU     (0x3:SHL:18)

;- Waveform Mode : External Event Effect on TIOA
AEEVT           EQU     (0x3:SHL:20)

;- Waveform Mode : Software Trigger Effect on TIOA
ASWTRG          EQU     (0x3:SHL:22)

;- Waveform Mode : RB Compare Effect on TIOB
BCPB            EQU     (0x3:SHL:24)

;- Waveform Mode : RC Compare Effect on TIOB
BCPC            EQU     (0x3:SHL:26)

;- Waveform Mode : External Event Effect on TIOB
BEEVT           EQU     (0x3:SHL:28)

;- Waveform Mode : Software Trigger Effect on TIOB
BSWTRG          EQU     (0x3:SHL:30)

;------------------------------------------------
;- Timer Counter Status Register Bits Definition
;------------------------------------------------
;- Counter Overflow Status
COVFS           EQU     0x01
;- Load Overrun Status
LOVRS           EQU     0x02
;- RA Compare Status
CPAS            EQU     0x04
;- RB Compare Status
CPBS            EQU     0x08
;- RC Compare Status
CPCS            EQU     0x10
;- RA Loading Status
LDRAS           EQU     0x20
;- RB Loading Status
LDRBS           EQU     0x40
;- External Trigger Status
ETRGS           EQU     0x80
;- Clock Status
CLKSTA          EQU     0x10000
;- TIOA Mirror
MTIOA           EQU     0x20000
;- TIOB Status
MTIOB           EQU     0x40000

;-------------------------------------------------------
;- Timer Counter Block Control Register Bits Definition
;-------------------------------------------------------
;- Synchronisation Trigger
TCSYNC          EQU     0x1

;----------------------------------------------------
;- Timer Counter Block Mode Register Bits Definition
;----------------------------------------------------
;- External Clock Signal 0 Selection
TC0XC0S         EQU     (0x3:SHL:0)

;- External Clock Signal 1 Selection
TC1XC1S         EQU     (0x3:SHL:2)

;- External Clock Signal 2 Selection
TC2XC2S         EQU     (0x3:SHL:4)

;--------------------------------
;- Device Dependancies Definition
;--------------------------------

    IF  :DEF:AT91M40400
NB_TC_BLOCK     EQU     1
TCB_BASE        EQU     0xFFFE0000
    ENDIF

                END