usart.inc

嵌入式系统开发用源代码 包含At91C arm芯片相关各种例程 包括整数性能测试,浮点测试,硬件驱动等

;-----------------------------------------------------------------------------
;-      ATMEL Microcontroller Software Support  -   ROUSSET -
;-----------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File Name            : usart.inc
;- Object               : USART Definition File.
;- Translator           : ARM Software Development Toolkit V2.11a
;-
;- 1.0 10/03/98 JCZ     : Creation
;- 2.0 21/10/98 JCZ     : Clean up.
;-----------------------------------------------------------------------------

;----------------
; USART Structure
;----------------
                ^       0
US_CR           #       4       ; Control Register
US_MR           #       4       ; Mode Register
US_IER          #       4       ; Interrupt Enable Register
US_IDR          #       4       ; Interrupt Disable Register
US_IMR          #       4       ; Interrupt Mask Register
US_CSR          #       4       ; Status Register
US_RHR          #       4       ; Receive Holding Register
US_THR          #       4       ; Transmit Holding Register
US_BRD          #       4       ; Baud Rate Generator Register
US_RTOR         #       4       ; Receive Time Out Register
US_TTGR         #       4       ; Transmit Time Guard Register
                #       4
US_RPR          #       4       ; Receive Pointer Register
US_RCR          #       4       ; Receive Counter Register
US_TPR          #       4       ; Transmit Pointer Register
US_TCR          #       4       ; Transmit Counter Register

;-------------------
;- Control Register
;-------------------
;- Reset Receiver
RSTRX           EQU     0x04
;- Reset Transmitter
RSTTX           EQU     0x08
;- Receiver Enable
RXEN            EQU     0x10
;- Receiver Disable
RXDIS           EQU     0x20
;- Transmitter Enable
TXEN            EQU     0x40
;- Transmitter Disable
TXDIS           EQU     0x80
;- Reset Status Bits
RSTSTA          EQU     0x100
;- Start Break
STTBRK          EQU     0x200
;- Stop Break
STPBRK          EQU     0x400
;- Start Timeout
STTTO           EQU     0x800
;- Send Address
SENDA           EQU     0x1000
;- Force Load
FORCEL          EQU     0x10000

;----------------
;- Mode Register
;----------------

;- Clock Selection
CLKS            EQU     0x30

;- Byte Length
CHRL            EQU     0xC0

;- Synchronous Mode Enable
SYNC            EQU     0x100

;- Parity Mode
PAR             EQU     (0x7:SHL:9)

;- Stop Bit Number
NBSTOP          EQU     (0x3:SHL:12)

;- Channel Mode
CHMODE          EQU     (0x3:SHL:14)

;- 9 Bit Mode
MODE9           EQU     0x20000

;- Baud Rate Output Enable
CLKO            EQU     0x40000

;--------------------------
;- Channel Status Register
;--------------------------

;- Receiver Ready
RXRDY           EQU     0x01

;- Transmitter Ready
TXRDY           EQU     0x02

;- Receiver Break
RXBRK           EQU     0x04

;- End of Receiver PDC Transfer
ENDRX           EQU     0x08

;- End of Transmitter PDC Transfer
ENDTX           EQU     0x10

;- Overrun Error
OVRE            EQU     0x20

;- Framing Error
FRAME           EQU     0x40

;- Parity Error
PARE            EQU     0x80

;- Receiver Timeout
TIMEOUT         EQU     0x100

;- Transmitter Empty
TXEMPTY         EQU     0x200

;- USART Handler Table Structure
                ^       0
ErrorMask       #       4
ErrorHandler    #       4
RxMask          #       4
RxHandler       #       4
TxMask          #       4
TxHandler       #       4

SIZE_USART_HANDLER_TABLE    #   0

;--------------------------------
;- Device Dependancies Definition
;--------------------------------

    IF  :DEF:AT91M40400

NB_USART        EQU     2
USART0_BASE     EQU     0xFFFD0000
USART1_BASE     EQU     0xFFFCC000

    ENDIF

                END