at91sam7x256_tdes.html

atmel at91sam7s和7x下

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<a name="TDES_IER"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_IER">AT91C_TDES_IER</a></i> 0xFFFA8010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TDES_DATRDY"></a><b>TDES_DATRDY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_DATRDY">AT91C_TDES_DATRDY</a></font></td><td><b>DATRDY</b><br>0 = No effect.<br>1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TDES_ENDRX"></a><b>TDES_ENDRX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_ENDRX">AT91C_TDES_ENDRX</a></font></td><td><b>PDC Read Buffer End</b><br>0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR.<br>1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TDES_ENDTX"></a><b>TDES_ENDTX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_ENDTX">AT91C_TDES_ENDTX</a></font></td><td><b>PDC Write Buffer End</b><br>0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR.<br>1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TDES_RXBUFF"></a><b>TDES_RXBUFF</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_RXBUFF">AT91C_TDES_RXBUFF</a></font></td><td><b>PDC Read Buffer Full</b><br>0 = TDES_RCR or TDES_RNCR has a value other than 0.<br>1 = Both TDES_RCR and TDES_RNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TDES_TXBUFE"></a><b>TDES_TXBUFE</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_TXBUFE">AT91C_TDES_TXBUFE</a></font></td><td><b>PDC Write Buffer Empty</b><br>0 = TDES_TCR or TDES_TNCR has a value other than 0.<br>1 = Both TDES_TCR and TDES_TNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TDES_URAD"></a><b>TDES_URAD</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_URAD">AT91C_TDES_URAD</a></font></td><td><b>Unspecified Register Access Detection</b><br>0 = No unspecified register access has been detected since the last SWRST.<br>1 = At least one unspecified register access has been detected since the last SWRST.</td></tr>
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<a name="TDES_IDR"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_IDR">AT91C_TDES_IDR</a></i> 0xFFFA8014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TDES_DATRDY"></a><b>TDES_DATRDY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_DATRDY">AT91C_TDES_DATRDY</a></font></td><td><b>DATRDY</b><br>0 = No effect.<br>1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TDES_ENDRX"></a><b>TDES_ENDRX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_ENDRX">AT91C_TDES_ENDRX</a></font></td><td><b>PDC Read Buffer End</b><br>0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR.<br>1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TDES_ENDTX"></a><b>TDES_ENDTX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_ENDTX">AT91C_TDES_ENDTX</a></font></td><td><b>PDC Write Buffer End</b><br>0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR.<br>1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TDES_RXBUFF"></a><b>TDES_RXBUFF</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_RXBUFF">AT91C_TDES_RXBUFF</a></font></td><td><b>PDC Read Buffer Full</b><br>0 = TDES_RCR or TDES_RNCR has a value other than 0.<br>1 = Both TDES_RCR and TDES_RNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TDES_TXBUFE"></a><b>TDES_TXBUFE</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_TXBUFE">AT91C_TDES_TXBUFE</a></font></td><td><b>PDC Write Buffer Empty</b><br>0 = TDES_TCR or TDES_TNCR has a value other than 0.<br>1 = Both TDES_TCR and TDES_TNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TDES_URAD"></a><b>TDES_URAD</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_URAD">AT91C_TDES_URAD</a></font></td><td><b>Unspecified Register Access Detection</b><br>0 = No unspecified register access has been detected since the last SWRST.<br>1 = At least one unspecified register access has been detected since the last SWRST.</td></tr>
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<a name="TDES_IMR"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_IMR">AT91C_TDES_IMR</a></i> 0xFFFA8018</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TDES_DATRDY"></a><b>TDES_DATRDY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_DATRDY">AT91C_TDES_DATRDY</a></font></td><td><b>DATRDY</b><br>0 = No effect.<br>1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TDES_ENDRX"></a><b>TDES_ENDRX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_ENDRX">AT91C_TDES_ENDRX</a></font></td><td><b>PDC Read Buffer End</b><br>0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR.<br>1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TDES_ENDTX"></a><b>TDES_ENDTX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_ENDTX">AT91C_TDES_ENDTX</a></font></td><td><b>PDC Write Buffer End</b><br>0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR.<br>1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TDES_RXBUFF"></a><b>TDES_RXBUFF</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_RXBUFF">AT91C_TDES_RXBUFF</a></font></td><td><b>PDC Read Buffer Full</b><br>0 = TDES_RCR or TDES_RNCR has a value other than 0.<br>1 = Both TDES_RCR and TDES_RNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TDES_TXBUFE"></a><b>TDES_TXBUFE</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_TXBUFE">AT91C_TDES_TXBUFE</a></font></td><td><b>PDC Write Buffer Empty</b><br>0 = TDES_TCR or TDES_TNCR has a value other than 0.<br>1 = Both TDES_TCR and TDES_TNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TDES_URAD"></a><b>TDES_URAD</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_URAD">AT91C_TDES_URAD</a></font></td><td><b>Unspecified Register Access Detection</b><br>0 = No unspecified register access has been detected since the last SWRST.<br>1 = At least one unspecified register access has been detected since the last SWRST.</td></tr>
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<a name="TDES_ISR"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_ISR  <i>Interrupt Status Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_ISR">AT91C_TDES_ISR</a></i> 0xFFFA801C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TDES_DATRDY"></a><b>TDES_DATRDY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_DATRDY">AT91C_TDES_DATRDY</a></font></td><td><b>DATRDY</b><br>0 = No effect.<br>1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TDES_ENDRX"></a><b>TDES_ENDRX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_ENDRX">AT91C_TDES_ENDRX</a></font></td><td><b>PDC Read Buffer End</b><br>0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR.<br>1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TDES_ENDTX"></a><b>TDES_ENDTX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_ENDTX">AT91C_TDES_ENDTX</a></font></td><td><b>PDC Write Buffer End</b><br>0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR.<br>1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TDES_RXBUFF"></a><b>TDES_RXBUFF</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_RXBUFF">AT91C_TDES_RXBUFF</a></font></td><td><b>PDC Read Buffer Full</b><br>0 = TDES_RCR or TDES_RNCR has a value other than 0.<br>1 = Both TDES_RCR and TDES_RNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TDES_TXBUFE"></a><b>TDES_TXBUFE</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_TXBUFE">AT91C_TDES_TXBUFE</a></font></td><td><b>PDC Write Buffer Empty</b><br>0 = TDES_TCR or TDES_TNCR has a value other than 0.<br>1 = Both TDES_TCR and TDES_TNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TDES_URAD"></a><b>TDES_URAD</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_URAD">AT91C_TDES_URAD</a></font></td><td><b>Unspecified Register Access Detection</b><br>0 = No unspecified register access has been detected since the last SWRST.<br>1 = At least one unspecified register access has been detected since the last SWRST.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13..12</td><td align="CENTER"><a name="TDES_URAT"></a><b>TDES_URAT</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_URAT">AT91C_TDES_URAT</a></font></td><td><b>Unspecified Register Access Type Status</b><br>Only the last Unspecified Register Access Type is available through the URAT field.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="TDES_URAT_IN_DAT_WRITE_DATPROC"></a><b>TDES_URAT_IN_DAT_WRITE_DATPROC</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC">AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC</a></font></td><td><br>Input data register written during the data processing in PDC mode.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="TDES_URAT_OUT_DAT_READ_DATPROC"></a><b>TDES_URAT_OUT_DAT_READ_DATPROC</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_URAT_OUT_DAT_READ_DATPROC">AT91C_TDES_URAT_OUT_DAT_READ_DATPROC</a></font></td><td><br>Output data register read during the data processing.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="TDES_URAT_MODEREG_WRITE_DATPROC"></a><b>TDES_URAT_MODEREG_WRITE_DATPROC</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_URAT_MODEREG_WRITE_DATPROC">AT91C_TDES_URAT_MODEREG_WRITE_DATPROC</a></font></td><td><br>Mode register written during the data processing.</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="TDES_URAT_WO_REG_READ"></a><b>TDES_URAT_WO_REG_READ</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_TDES_URAT_WO_REG_READ">AT91C_TDES_URAT_WO_REG_READ</a></font></td><td><br>Write-only register read access.</td></tr>
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<a name="TDES_KEY1WxR"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_KEY1WxR  <i>Key 1 Word x Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_KEY1WxR">AT91C_TDES_KEY1WxR</a></i> 0xFFFA8020</font></null></ul><br>Key 1 Word x: The two 32-bit Key 1 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption.<a name="TDES_KEY2WxR"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_KEY2WxR  <i>Key 2 Word x Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_KEY2WxR">AT91C_TDES_KEY2WxR</a></i> 0xFFFA8028</font></null></ul><br>Key 2 Word x: The two 32-bit Key 2 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption.<a name="TDES_KEY3WxR"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_KEY3WxR  <i>Key 3 Word x Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_KEY3WxR">AT91C_TDES_KEY3WxR</a></i> 0xFFFA8030</font></null></ul><br>Key 3 Word x: The two 32-bit Key 3 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption.<a name="TDES_IDATAxR"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_IDATAxR  <i>Input Data x Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_IDATAxR">AT91C_TDES_IDATAxR</a></i> 0xFFFA8040</font></null></ul><br>The two 32-bit Input Data registers allow to set the 64-bit data block used for encryption/decryption.<a name="TDES_ODATAxR"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_ODATAxR  <i>Output Data x Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_ODATAxR">AT91C_TDES_ODATAxR</a></i> 0xFFFA8050</font></null></ul><br>The two 32-bit Output Data registers contain the 64-bit data block which has been encrypted/decrypted.<a name="TDES_IVxR"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_IVxR  <i>Initialization Vector x Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_IVxR">AT91C_TDES_IVxR</a></i> 0xFFFA8060</font></null></ul><br>The two 32-bit Initialization Vector registers allow to set the 64-bit Initialization Vector data block, which is used by some modes of operation as an additional initial input.<a name="TDES_VR"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> TDES_VR  <i>TDES Version Register</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="AT91SAM7X256_h.html#AT91C_TDES_VR">AT91C_TDES_VR</a></i> 0xFFFA80FC</font></null></ul><a name="TDES_PDC"></a><h4><a href="#TDES">TDES</a>: <i><a href="AT91SAM7X256_h.html#AT91S_PDC">AT91S_PDC</a></i> TDES_PDC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>TDES</b> <i><a href="#AT91C_TDES_TDES">AT91C_TDES_TDES</a></i> 0xFFFA8100</font></null></ul></null><hr></html>