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atmel at91sam7s和7x下

<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_CKG_HIGH"></a><b>SSC_CKG_HIGH</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_CKG_HIGH">AT91C_SSC_CKG_HIGH</a></font></td><td><br>Receive/Transmit Clock enabled only if RF High</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">11..8</td><td align="CENTER"><a name="SSC_START"></a><b>SSC_START</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_START">AT91C_SSC_START</a></font></td><td><b>Receive/Transmit Start Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_START_CONTINOUS"></a><b>SSC_START_CONTINOUS</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_START_CONTINOUS">AT91C_SSC_START_CONTINOUS</a></font></td><td><br>Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_START_TX"></a><b>SSC_START_TX</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_START_TX">AT91C_SSC_START_TX</a></font></td><td><br>Transmit/Receive start</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_START_LOW_RF"></a><b>SSC_START_LOW_RF</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_START_LOW_RF">AT91C_SSC_START_LOW_RF</a></font></td><td><br>Detection of a low level on RF input</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SSC_START_HIGH_RF"></a><b>SSC_START_HIGH_RF</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_START_HIGH_RF">AT91C_SSC_START_HIGH_RF</a></font></td><td><br>Detection of a high level on RF input</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SSC_START_FALL_RF"></a><b>SSC_START_FALL_RF</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_START_FALL_RF">AT91C_SSC_START_FALL_RF</a></font></td><td><br>Detection of a falling edge on RF input</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SSC_START_RISE_RF"></a><b>SSC_START_RISE_RF</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_START_RISE_RF">AT91C_SSC_START_RISE_RF</a></font></td><td><br>Detection of a rising edge on RF input</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="SSC_START_LEVEL_RF"></a><b>SSC_START_LEVEL_RF</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_START_LEVEL_RF">AT91C_SSC_START_LEVEL_RF</a></font></td><td><br>Detection of any level change on RF input</td></tr>
<tr><td align="CENTER">7</td><td align="CENTER"><a name="SSC_START_EDGE_RF"></a><b>SSC_START_EDGE_RF</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_START_EDGE_RF">AT91C_SSC_START_EDGE_RF</a></font></td><td><br>Detection of any edge on RF input</td></tr>
<tr><td align="CENTER">8</td><td align="CENTER"><a name="SSC_START_0"></a><b>SSC_START_0</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_START_0">AT91C_SSC_START_0</a></font></td><td><br>Compare 0</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">23..16</td><td align="CENTER"><a name="SSC_STTDLY"></a><b>SSC_STTDLY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_STTDLY">AT91C_SSC_STTDLY</a></font></td><td><b>Receive/Transmit Start Delay</b><br>If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception/transmission.<br>When the Receiver/Transmitter is programmed to start synchronously with the Transmitter/Receiver, the delay is also applied.<br>Please Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive/Transmit Sync Data) reception.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..24</td><td align="CENTER"><a name="SSC_PERIOD"></a><b>SSC_PERIOD</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_PERIOD">AT91C_SSC_PERIOD</a></font></td><td><b>Receive/Transmit Period Divider Selection</b><br>This field selects the divider to apply to the selected Receive/Transmit Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive/Transmit Clock.</td></tr>
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<a name="SSC_TFMR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> SSC_TFMR  <i>Transmit Frame Mode Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7X256_h.html#AT91C_SSC_TFMR">AT91C_SSC_TFMR</a></i> 0xFFFD401C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">4..0</td><td align="CENTER"><a name="SSC_DATLEN"></a><b>SSC_DATLEN</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_DATLEN">AT91C_SSC_DATLEN</a></font></td><td><b>Data Length</b><br>The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver/Transmitter. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_DATDEF"></a><b>SSC_DATDEF</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_DATDEF">AT91C_SSC_DATDEF</a></font></td><td><b>Data Default Value</b><br>This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_MSBF"></a><b>SSC_MSBF</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_MSBF">AT91C_SSC_MSBF</a></font></td><td><b>Most Significant Bit First</b><br>0: The lowest significant bit of the data register is sampled first in the bit stream.<br>1: The most significant bit of the data register is sampled first in the bit stream.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..8</td><td align="CENTER"><a name="SSC_DATNB"></a><b>SSC_DATNB</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_DATNB">AT91C_SSC_DATNB</a></font></td><td><b>Data Number per Frame</b><br>This field defines the number of data words to be received/transfered after each transfer start. If 0, only 1 data word is transferred. Up to 16 data words can be transferred.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19..16</td><td align="CENTER"><a name="SSC_FSLEN"></a><b>SSC_FSLEN</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_FSLEN">AT91C_SSC_FSLEN</a></font></td><td><b>Receive/Transmit Frame Sync length</b><br>Receive:<br>This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. If 0, the Receive Frame Sync Sig-nal is generated during one Receive Clock period and up to a 16-clock period pulse length is possible.<br>Transmit:<br>This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. If 0, the Transmit Frame Sync signal is generated during one Transmit Clock period and up to 16 clock period pulse length is possible.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..20</td><td align="CENTER"><a name="SSC_FSOS"></a><b>SSC_FSOS</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_FSOS">AT91C_SSC_FSOS</a></font></td><td><b>Receive/Transmit Frame Sync Output Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_FSOS_NONE"></a><b>SSC_FSOS_NONE</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_FSOS_NONE">AT91C_SSC_FSOS_NONE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_FSOS_NEGATIVE"></a><b>SSC_FSOS_NEGATIVE</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_FSOS_NEGATIVE">AT91C_SSC_FSOS_NEGATIVE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Negative Pulse</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_FSOS_POSITIVE"></a><b>SSC_FSOS_POSITIVE</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_FSOS_POSITIVE">AT91C_SSC_FSOS_POSITIVE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Positive Pulse</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SSC_FSOS_LOW"></a><b>SSC_FSOS_LOW</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_FSOS_LOW">AT91C_SSC_FSOS_LOW</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SSC_FSOS_HIGH"></a><b>SSC_FSOS_HIGH</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_FSOS_HIGH">AT91C_SSC_FSOS_HIGH</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SSC_FSOS_TOGGLE"></a><b>SSC_FSOS_TOGGLE</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_FSOS_TOGGLE">AT91C_SSC_FSOS_TOGGLE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">23</td><td align="CENTER"><a name="SSC_FSDEN"></a><b>SSC_FSDEN</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_FSDEN">AT91C_SSC_FSDEN</a></font></td><td><b>Frame Sync Data Enable</b><br>0: The TD line is driven with the default value during the Transmit Frame Sync signal.<br>1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">24</td><td align="CENTER"><a name="SSC_FSEDGE"></a><b>SSC_FSEDGE</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_FSEDGE">AT91C_SSC_FSEDGE</a></font></td><td><b>Frame Sync Edge Detection</b><br>Determines which edge on Frame Sync will generate the interrupt RXSYN/TXSYN in the SSC Status Register.<br>0: Positive Edge Detection<br>1: Negative Edge Detection</td></tr>
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<a name="SSC_RHR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> SSC_RHR  <i>Receive Holding Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7X256_h.html#AT91C_SSC_RHR">AT91C_SSC_RHR</a></i> 0xFFFD4020</font></null></ul><br>Right aligned regardless of the number of data bits defined by DATLEN in SSC_RMR<a name="SSC_THR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> SSC_THR  <i>Transmit Holding Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7X256_h.html#AT91C_SSC_THR">AT91C_SSC_THR</a></i> 0xFFFD4024</font></null></ul><br>Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR<a name="SSC_RSHR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> SSC_RSHR  <i>Receive Sync Holding Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7X256_h.html#AT91C_SSC_RSHR">AT91C_SSC_RSHR</a></i> 0xFFFD4030</font></null></ul><br>Receive Synchronization Data<a name="SSC_TSHR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> SSC_TSHR  <i>Transmit Sync Holding Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7X256_h.html#AT91C_SSC_TSHR">AT91C_SSC_TSHR</a></i> 0xFFFD4034</font></null></ul><br>Transmit Synchronization Data<a name="SSC_SR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> SSC_SR  <i>Status Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7X256_h.html#AT91C_SSC_SR">AT91C_SSC_SR</a></i> 0xFFFD4040</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SSC_TXRDY"></a><b>SSC_TXRDY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_TXRDY">AT91C_SSC_TXRDY</a></font></td><td><b>Transmit Ready</b><br>0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).<br>1: SSC_THR is empty.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SSC_TXEMPTY"></a><b>SSC_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_TXEMPTY">AT91C_SSC_TXEMPTY</a></font></td><td><b>Transmit Empty</b><br>0: Data remains in SSC_THR or is currently transmitted from TSR.<br>1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SSC_ENDTX"></a><b>SSC_ENDTX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_ENDTX">AT91C_SSC_ENDTX</a></font></td><td><b>End Of Transmission</b><br>0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.<br>1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SSC_TXBUFE"></a><b>SSC_TXBUFE</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_TXBUFE">AT91C_SSC_TXBUFE</a></font></td><td><b>Transmit Buffer Empty</b><br>0: SSC_TCR or SSC_TNCR have a value other than 0.<br>1: Both SSC_TCR and SSC_TNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SSC_RXRDY"></a><b>SSC_RXRDY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_RXRDY">AT91C_SSC_RXRDY</a></font></td><td><b>Receive Ready</b><br>0: SSC_RHR is empty.<br>1: Data has been received and loaded in SSC_RHR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_OVRUN"></a><b>SSC_OVRUN</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_OVRUN">AT91C_SSC_OVRUN</a></font></td><td><b>Receive Overrun</b><br>0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.<br>1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SSC_ENDRX"></a><b>SSC_ENDRX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_SSC_ENDRX">AT91C_SSC_ENDRX</a></font></td><td><b>End of Reception</b><br>0: Data is written on the Receive Counter Register or Receive Next Counter Register.<br>1: End of PDC transfer when Receive Counter Register has arrived at zero.</td></tr>