at91sam7x256_aes.html

atmel at91sam7s和7x下

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<a name="AES_IER"></a><h4><a href="#AES">AES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> AES_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>AES</b> <i><a href="AT91SAM7X256_h.html#AT91C_AES_IER">AT91C_AES_IER</a></i> 0xFFFA4010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="AES_DATRDY"></a><b>AES_DATRDY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_DATRDY">AT91C_AES_DATRDY</a></font></td><td><b>DATRDY</b><br>0 = No effect.<br>1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="AES_ENDRX"></a><b>AES_ENDRX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_ENDRX">AT91C_AES_ENDRX</a></font></td><td><b>PDC Read Buffer End</b><br>0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR.<br>1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="AES_ENDTX"></a><b>AES_ENDTX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_ENDTX">AT91C_AES_ENDTX</a></font></td><td><b>PDC Write Buffer End</b><br>0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR.<br>1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="AES_RXBUFF"></a><b>AES_RXBUFF</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_RXBUFF">AT91C_AES_RXBUFF</a></font></td><td><b>PDC Read Buffer Full</b><br>0 = AES_RCR or AES_RNCR has a value other than 0.<br>1 = Both AES_RCR and AES_RNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="AES_TXBUFE"></a><b>AES_TXBUFE</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_TXBUFE">AT91C_AES_TXBUFE</a></font></td><td><b>PDC Write Buffer Empty</b><br>0 = AES_TCR or AES_TNCR has a value other than 0.<br>1 = Both AES_TCR and AES_TNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="AES_URAD"></a><b>AES_URAD</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAD">AT91C_AES_URAD</a></font></td><td><b>Unspecified Register Access Detection</b><br>0 = No unspecified register access has been detected since the last SWRST.<br>1 = At least one unspecified register access has been detected since the last SWRST.</td></tr>
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<a name="AES_IDR"></a><h4><a href="#AES">AES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> AES_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>AES</b> <i><a href="AT91SAM7X256_h.html#AT91C_AES_IDR">AT91C_AES_IDR</a></i> 0xFFFA4014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="AES_DATRDY"></a><b>AES_DATRDY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_DATRDY">AT91C_AES_DATRDY</a></font></td><td><b>DATRDY</b><br>0 = No effect.<br>1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="AES_ENDRX"></a><b>AES_ENDRX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_ENDRX">AT91C_AES_ENDRX</a></font></td><td><b>PDC Read Buffer End</b><br>0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR.<br>1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="AES_ENDTX"></a><b>AES_ENDTX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_ENDTX">AT91C_AES_ENDTX</a></font></td><td><b>PDC Write Buffer End</b><br>0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR.<br>1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="AES_RXBUFF"></a><b>AES_RXBUFF</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_RXBUFF">AT91C_AES_RXBUFF</a></font></td><td><b>PDC Read Buffer Full</b><br>0 = AES_RCR or AES_RNCR has a value other than 0.<br>1 = Both AES_RCR and AES_RNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="AES_TXBUFE"></a><b>AES_TXBUFE</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_TXBUFE">AT91C_AES_TXBUFE</a></font></td><td><b>PDC Write Buffer Empty</b><br>0 = AES_TCR or AES_TNCR has a value other than 0.<br>1 = Both AES_TCR and AES_TNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="AES_URAD"></a><b>AES_URAD</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAD">AT91C_AES_URAD</a></font></td><td><b>Unspecified Register Access Detection</b><br>0 = No unspecified register access has been detected since the last SWRST.<br>1 = At least one unspecified register access has been detected since the last SWRST.</td></tr>
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<a name="AES_IMR"></a><h4><a href="#AES">AES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> AES_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>AES</b> <i><a href="AT91SAM7X256_h.html#AT91C_AES_IMR">AT91C_AES_IMR</a></i> 0xFFFA4018</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="AES_DATRDY"></a><b>AES_DATRDY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_DATRDY">AT91C_AES_DATRDY</a></font></td><td><b>DATRDY</b><br>0 = No effect.<br>1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="AES_ENDRX"></a><b>AES_ENDRX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_ENDRX">AT91C_AES_ENDRX</a></font></td><td><b>PDC Read Buffer End</b><br>0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR.<br>1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="AES_ENDTX"></a><b>AES_ENDTX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_ENDTX">AT91C_AES_ENDTX</a></font></td><td><b>PDC Write Buffer End</b><br>0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR.<br>1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="AES_RXBUFF"></a><b>AES_RXBUFF</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_RXBUFF">AT91C_AES_RXBUFF</a></font></td><td><b>PDC Read Buffer Full</b><br>0 = AES_RCR or AES_RNCR has a value other than 0.<br>1 = Both AES_RCR and AES_RNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="AES_TXBUFE"></a><b>AES_TXBUFE</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_TXBUFE">AT91C_AES_TXBUFE</a></font></td><td><b>PDC Write Buffer Empty</b><br>0 = AES_TCR or AES_TNCR has a value other than 0.<br>1 = Both AES_TCR and AES_TNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="AES_URAD"></a><b>AES_URAD</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAD">AT91C_AES_URAD</a></font></td><td><b>Unspecified Register Access Detection</b><br>0 = No unspecified register access has been detected since the last SWRST.<br>1 = At least one unspecified register access has been detected since the last SWRST.</td></tr>
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<a name="AES_ISR"></a><h4><a href="#AES">AES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> AES_ISR  <i>Interrupt Status Register</i></h4><ul><null><font size="-2"><li><b>AES</b> <i><a href="AT91SAM7X256_h.html#AT91C_AES_ISR">AT91C_AES_ISR</a></i> 0xFFFA401C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="AES_DATRDY"></a><b>AES_DATRDY</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_DATRDY">AT91C_AES_DATRDY</a></font></td><td><b>DATRDY</b><br>0 = No effect.<br>1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="AES_ENDRX"></a><b>AES_ENDRX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_ENDRX">AT91C_AES_ENDRX</a></font></td><td><b>PDC Read Buffer End</b><br>0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR.<br>1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="AES_ENDTX"></a><b>AES_ENDTX</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_ENDTX">AT91C_AES_ENDTX</a></font></td><td><b>PDC Write Buffer End</b><br>0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR.<br>1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="AES_RXBUFF"></a><b>AES_RXBUFF</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_RXBUFF">AT91C_AES_RXBUFF</a></font></td><td><b>PDC Read Buffer Full</b><br>0 = AES_RCR or AES_RNCR has a value other than 0.<br>1 = Both AES_RCR and AES_RNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="AES_TXBUFE"></a><b>AES_TXBUFE</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_TXBUFE">AT91C_AES_TXBUFE</a></font></td><td><b>PDC Write Buffer Empty</b><br>0 = AES_TCR or AES_TNCR has a value other than 0.<br>1 = Both AES_TCR and AES_TNCR has a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="AES_URAD"></a><b>AES_URAD</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAD">AT91C_AES_URAD</a></font></td><td><b>Unspecified Register Access Detection</b><br>0 = No unspecified register access has been detected since the last SWRST.<br>1 = At least one unspecified register access has been detected since the last SWRST.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">14..12</td><td align="CENTER"><a name="AES_URAT"></a><b>AES_URAT</b><font size="-2"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAT">AT91C_AES_URAT</a></font></td><td><b>Unspecified Register Access Type Status</b><br>Only the last Unspecified Register Access Type is available through the URAT field.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="AES_URAT_IN_DAT_WRITE_DATPROC"></a><b>AES_URAT_IN_DAT_WRITE_DATPROC</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAT_IN_DAT_WRITE_DATPROC">AT91C_AES_URAT_IN_DAT_WRITE_DATPROC</a></font></td><td><br>Input data register written during the data processing in PDC mode.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="AES_URAT_OUT_DAT_READ_DATPROC"></a><b>AES_URAT_OUT_DAT_READ_DATPROC</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAT_OUT_DAT_READ_DATPROC">AT91C_AES_URAT_OUT_DAT_READ_DATPROC</a></font></td><td><br>Output data register read during the data processing.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="AES_URAT_MODEREG_WRITE_DATPROC"></a><b>AES_URAT_MODEREG_WRITE_DATPROC</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAT_MODEREG_WRITE_DATPROC">AT91C_AES_URAT_MODEREG_WRITE_DATPROC</a></font></td><td><br>Mode register written during the data processing.</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="AES_URAT_OUT_DAT_READ_SUBKEY"></a><b>AES_URAT_OUT_DAT_READ_SUBKEY</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAT_OUT_DAT_READ_SUBKEY">AT91C_AES_URAT_OUT_DAT_READ_SUBKEY</a></font></td><td><br>Output data register read during the sub-keys generation.</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="AES_URAT_MODEREG_WRITE_SUBKEY"></a><b>AES_URAT_MODEREG_WRITE_SUBKEY</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAT_MODEREG_WRITE_SUBKEY">AT91C_AES_URAT_MODEREG_WRITE_SUBKEY</a></font></td><td><br>Mode register written during the sub-keys generation.</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="AES_URAT_WO_REG_READ"></a><b>AES_URAT_WO_REG_READ</b><font size="-1"><br><a href="AT91SAM7X256_h.html#AT91C_AES_URAT_WO_REG_READ">AT91C_AES_URAT_WO_REG_READ</a></font></td><td><br>Write-only register read access.</td></tr>
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<a name="AES_KEYWxR"></a><h4><a href="#AES">AES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> AES_KEYWxR  <i>Key Word x Register</i></h4><ul><null><font size="-2"><li><b>AES</b> <i><a href="AT91SAM7X256_h.html#AT91C_AES_KEYWxR">AT91C_AES_KEYWxR</a></i> 0xFFFA4020</font></null></ul><br>Key Word x: The four 32-bit Key registers allow to set the 128-bit cryptographic key used for encryption/decryption.<a name="AES_IDATAxR"></a><h4><a href="#AES">AES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> AES_IDATAxR  <i>Input Data x Register</i></h4><ul><null><font size="-2"><li><b>AES</b> <i><a href="AT91SAM7X256_h.html#AT91C_AES_IDATAxR">AT91C_AES_IDATAxR</a></i> 0xFFFA4040</font></null></ul><br>The four 32-bit Input Data registers allow to set the 128-bit data block used for encryption/decryption.<a name="AES_ODATAxR"></a><h4><a href="#AES">AES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> AES_ODATAxR  <i>Output Data x Register</i></h4><ul><null><font size="-2"><li><b>AES</b> <i><a href="AT91SAM7X256_h.html#AT91C_AES_ODATAxR">AT91C_AES_ODATAxR</a></i> 0xFFFA4050</font></null></ul><br>The four 32-bit Output Data registers contain the 128-bit data block which has been encrypted/decrypted.<a name="AES_IVxR"></a><h4><a href="#AES">AES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> AES_IVxR  <i>Initialization Vector x Register</i></h4><ul><null><font size="-2"><li><b>AES</b> <i><a href="AT91SAM7X256_h.html#AT91C_AES_IVxR">AT91C_AES_IVxR</a></i> 0xFFFA4060</font></null></ul><br>The four 32-bit Initialization Vector registers allow to set the 128-bit Initialization Vector data block, which is used by some modes of operation as an additional initial input.<a name="AES_VR"></a><h4><a href="#AES">AES</a>: <i><a href="AT91SAM7X256_h.html#AT91_REG">AT91_REG</a></i> AES_VR  <i>AES Version Register</i></h4><ul><null><font size="-2"><li><b>AES</b> <i><a href="AT91SAM7X256_h.html#AT91C_AES_VR">AT91C_AES_VR</a></i> 0xFFFA40FC</font></null></ul><a name="AES_PDC"></a><h4><a href="#AES">AES</a>: <i><a href="AT91SAM7X256_h.html#AT91S_PDC">AT91S_PDC</a></i> AES_PDC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>AES</b> <i><a href="#AT91C_AES_AES">AT91C_AES_AES</a></i> 0xFFFA4100</font></null></ul></null><hr></html>