at91sam7s128_adc.html

atmel at91sam7s和7x下

<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="ADC_DRDY"></a><b>ADC_DRDY</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_DRDY">AT91C_ADC_DRDY</a></font></td><td><b>Data Ready</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="ADC_GOVRE"></a><b>ADC_GOVRE</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_GOVRE">AT91C_ADC_GOVRE</a></font></td><td><b>General Overrun</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="ADC_ENDRX"></a><b>ADC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_ENDRX">AT91C_ADC_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="ADC_RXBUFF"></a><b>ADC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_RXBUFF">AT91C_ADC_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
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<a name="ADC_IMR"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> ADC_IMR  <i>ADC Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S128_h.html#AT91C_ADC_IMR">AT91C_ADC_IMR</a></i> 0xFFFD802C</font></null></ul><br>0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ADC_EOC0"></a><b>ADC_EOC0</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_EOC0">AT91C_ADC_EOC0</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="ADC_EOC1"></a><b>ADC_EOC1</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_EOC1">AT91C_ADC_EOC1</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="ADC_EOC2"></a><b>ADC_EOC2</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_EOC2">AT91C_ADC_EOC2</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="ADC_EOC3"></a><b>ADC_EOC3</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_EOC3">AT91C_ADC_EOC3</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="ADC_EOC4"></a><b>ADC_EOC4</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_EOC4">AT91C_ADC_EOC4</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="ADC_EOC5"></a><b>ADC_EOC5</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_EOC5">AT91C_ADC_EOC5</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="ADC_EOC6"></a><b>ADC_EOC6</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_EOC6">AT91C_ADC_EOC6</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="ADC_EOC7"></a><b>ADC_EOC7</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_EOC7">AT91C_ADC_EOC7</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="ADC_OVRE0"></a><b>ADC_OVRE0</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_OVRE0">AT91C_ADC_OVRE0</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="ADC_OVRE1"></a><b>ADC_OVRE1</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_OVRE1">AT91C_ADC_OVRE1</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="ADC_OVRE2"></a><b>ADC_OVRE2</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_OVRE2">AT91C_ADC_OVRE2</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="ADC_OVRE3"></a><b>ADC_OVRE3</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_OVRE3">AT91C_ADC_OVRE3</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="ADC_OVRE4"></a><b>ADC_OVRE4</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_OVRE4">AT91C_ADC_OVRE4</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="ADC_OVRE5"></a><b>ADC_OVRE5</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_OVRE5">AT91C_ADC_OVRE5</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">14</td><td align="CENTER"><a name="ADC_OVRE6"></a><b>ADC_OVRE6</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_OVRE6">AT91C_ADC_OVRE6</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15</td><td align="CENTER"><a name="ADC_OVRE7"></a><b>ADC_OVRE7</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_OVRE7">AT91C_ADC_OVRE7</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="ADC_DRDY"></a><b>ADC_DRDY</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_DRDY">AT91C_ADC_DRDY</a></font></td><td><b>Data Ready</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="ADC_GOVRE"></a><b>ADC_GOVRE</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_GOVRE">AT91C_ADC_GOVRE</a></font></td><td><b>General Overrun</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="ADC_ENDRX"></a><b>ADC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_ENDRX">AT91C_ADC_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="ADC_RXBUFF"></a><b>ADC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_RXBUFF">AT91C_ADC_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
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<a name="ADC_CDR0"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR0  <i>ADC Channel Data Register 0</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S128_h.html#AT91C_ADC_CDR0">AT91C_ADC_CDR0</a></i> 0xFFFD8030</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
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<a name="ADC_CDR1"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR1  <i>ADC Channel Data Register 1</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S128_h.html#AT91C_ADC_CDR1">AT91C_ADC_CDR1</a></i> 0xFFFD8034</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
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<a name="ADC_CDR2"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR2  <i>ADC Channel Data Register 2</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S128_h.html#AT91C_ADC_CDR2">AT91C_ADC_CDR2</a></i> 0xFFFD8038</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
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<a name="ADC_CDR3"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR3  <i>ADC Channel Data Register 3</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S128_h.html#AT91C_ADC_CDR3">AT91C_ADC_CDR3</a></i> 0xFFFD803C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
</null></table>
<a name="ADC_CDR4"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR4  <i>ADC Channel Data Register 4</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S128_h.html#AT91C_ADC_CDR4">AT91C_ADC_CDR4</a></i> 0xFFFD8040</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
</null></table>
<a name="ADC_CDR5"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR5  <i>ADC Channel Data Register 5</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S128_h.html#AT91C_ADC_CDR5">AT91C_ADC_CDR5</a></i> 0xFFFD8044</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
</null></table>
<a name="ADC_CDR6"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR6  <i>ADC Channel Data Register 6</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S128_h.html#AT91C_ADC_CDR6">AT91C_ADC_CDR6</a></i> 0xFFFD8048</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
</null></table>
<a name="ADC_CDR7"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR7  <i>ADC Channel Data Register 7</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S128_h.html#AT91C_ADC_CDR7">AT91C_ADC_CDR7</a></i> 0xFFFD804C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
</null></table>
<a name="ADC_PDC"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S128_h.html#AT91S_PDC">AT91S_PDC</a></i> ADC_PDC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="#AT91C_ADC_ADC">AT91C_ADC_ADC</a></i> 0xFFFD8100</font></null></ul></null><hr></html>