at91sam7s128_pwmc_ch.html

atmel at91sam7s和7x下

<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xC</b></font></td><td><font size="-1"><a href="AT91SAM7S128_PWMC_CH.html#PWMC_CCNTR">PWMC_CCNTR</a></font></td><td><font size="-1">Channel Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10</b></font></td><td><font size="-1"><a href="AT91SAM7S128_PWMC_CH.html#PWMC_CUPDR">PWMC_CUPDR</a></font></td><td><font size="-1">Channel Update Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x14</b></font></td><td><font size="-1">PWMC_Reserved[3] (<a href="#PWMC_RESERVED">PWMC_RESERVED</a>)</font></td><td><font size="-1">Reserved</font></td></tr>
</null></table><br></null><h2>PWMC_CH Register Description</h2>
<null><a name="PWMC_CMR"></a><h4><a href="#PWMC_CH">PWMC_CH</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> PWMC_CMR  <i>Channel Mode Register</i></h4><ul><null><font size="-2"><li><b>PWMC_CH3</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH3_CMR">AT91C_PWMC_CH3_CMR</a></i> 0xFFFCC260</font><font size="-2"><li><b>PWMC_CH2</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH2_CMR">AT91C_PWMC_CH2_CMR</a></i> 0xFFFCC240</font><font size="-2"><li><b>PWMC_CH1</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH1_CMR">AT91C_PWMC_CH1_CMR</a></i> 0xFFFCC220</font><font size="-2"><li><b>PWMC_CH0</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH0_CMR">AT91C_PWMC_CH0_CMR</a></i> 0xFFFCC200</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">3..0</td><td align="CENTER"><a name="PWMC_CPRE"></a><b>PWMC_CPRE</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CPRE">AT91C_PWMC_CPRE</a></font></td><td><b>Channel Pre-scaler : PWMC_CLKx</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="PWMC_CPRE_MCK"></a><b>PWMC_CPRE_MCK</b><font size="-1"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CPRE_MCK">AT91C_PWMC_CPRE_MCK</a></font></td><td></td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="PWMC_CPRE_MCK/2"></a><b>PWMC_CPRE_MCK/2</b><font size="-1"><br><a href="#AT91C_PWMC_CPRE_MCK/2">AT91C_PWMC_CPRE_MCK/2</a></font></td><td></td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="PWMC_CPRE_MCK/4"></a><b>PWMC_CPRE_MCK/4</b><font size="-1"><br><a href="#AT91C_PWMC_CPRE_MCK/4">AT91C_PWMC_CPRE_MCK/4</a></font></td><td></td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="PWMC_CPRE_MCK/8"></a><b>PWMC_CPRE_MCK/8</b><font size="-1"><br><a href="#AT91C_PWMC_CPRE_MCK/8">AT91C_PWMC_CPRE_MCK/8</a></font></td><td></td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="PWMC_CPRE_MCK/16"></a><b>PWMC_CPRE_MCK/16</b><font size="-1"><br><a href="#AT91C_PWMC_CPRE_MCK/16">AT91C_PWMC_CPRE_MCK/16</a></font></td><td></td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="PWMC_CPRE_MCK/32"></a><b>PWMC_CPRE_MCK/32</b><font size="-1"><br><a href="#AT91C_PWMC_CPRE_MCK/32">AT91C_PWMC_CPRE_MCK/32</a></font></td><td></td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="PWMC_CPRE_MCK/64"></a><b>PWMC_CPRE_MCK/64</b><font size="-1"><br><a href="#AT91C_PWMC_CPRE_MCK/64">AT91C_PWMC_CPRE_MCK/64</a></font></td><td></td></tr>
<tr><td align="CENTER">7</td><td align="CENTER"><a name="PWMC_CPRE_MCK/128"></a><b>PWMC_CPRE_MCK/128</b><font size="-1"><br><a href="#AT91C_PWMC_CPRE_MCK/128">AT91C_PWMC_CPRE_MCK/128</a></font></td><td></td></tr>
<tr><td align="CENTER">8</td><td align="CENTER"><a name="PWMC_CPRE_MCK/256"></a><b>PWMC_CPRE_MCK/256</b><font size="-1"><br><a href="#AT91C_PWMC_CPRE_MCK/256">AT91C_PWMC_CPRE_MCK/256</a></font></td><td></td></tr>
<tr><td align="CENTER">9</td><td align="CENTER"><a name="PWMC_CPRE_MCK/512"></a><b>PWMC_CPRE_MCK/512</b><font size="-1"><br><a href="#AT91C_PWMC_CPRE_MCK/512">AT91C_PWMC_CPRE_MCK/512</a></font></td><td></td></tr>
<tr><td align="CENTER">10</td><td align="CENTER"><a name="PWMC_CPRE_MCK/1024"></a><b>PWMC_CPRE_MCK/1024</b><font size="-1"><br><a href="#AT91C_PWMC_CPRE_MCK/1024">AT91C_PWMC_CPRE_MCK/1024</a></font></td><td></td></tr>
<tr><td align="CENTER">11</td><td align="CENTER"><a name="PWMC_CPRE_MCKA"></a><b>PWMC_CPRE_MCKA</b><font size="-1"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CPRE_MCKA">AT91C_PWMC_CPRE_MCKA</a></font></td><td></td></tr>
<tr><td align="CENTER">12</td><td align="CENTER"><a name="PWMC_CPRE_MCKB"></a><b>PWMC_CPRE_MCKB</b><font size="-1"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CPRE_MCKB">AT91C_PWMC_CPRE_MCKB</a></font></td><td></td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="PWMC_CALG"></a><b>PWMC_CALG</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CALG">AT91C_PWMC_CALG</a></font></td><td><b>Channel Alignment</b><br>0: The period is left aligned. <br>1: The period is center aligned.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="PWMC_CPOL"></a><b>PWMC_CPOL</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CPOL">AT91C_PWMC_CPOL</a></font></td><td><b>Channel Polarity</b><br>0: The period starts by a low level. <br>1: The period starts by a high level.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="PWMC_CPD"></a><b>PWMC_CPD</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CPD">AT91C_PWMC_CPD</a></font></td><td><b>Channel Update Period</b><br>0: Writting to the PWMC_CUPDx will notify the duty cycle at the next period start event.<br>1: Writting to the PWMC_CUPDx will notify the period at the next period start event.</td></tr>
</null></table>
<a name="PWMC_CDTYR"></a><h4><a href="#PWMC_CH">PWMC_CH</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> PWMC_CDTYR  <i>Channel Duty Cycle Register</i></h4><ul><null><font size="-2"><li><b>PWMC_CH3</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH3_CDTYR">AT91C_PWMC_CH3_CDTYR</a></i> 0xFFFCC264</font><font size="-2"><li><b>PWMC_CH2</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH2_CDTYR">AT91C_PWMC_CH2_CDTYR</a></i> 0xFFFCC244</font><font size="-2"><li><b>PWMC_CH1</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH1_CDTYR">AT91C_PWMC_CH1_CDTYR</a></i> 0xFFFCC224</font><font size="-2"><li><b>PWMC_CH0</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH0_CDTYR">AT91C_PWMC_CH0_CDTYR</a></i> 0xFFFCC204</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">31..0</td><td align="CENTER"><a name="PWMC_CDTY"></a><b>PWMC_CDTY</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CDTY">AT91C_PWMC_CDTY</a></font></td><td><b>Channel Duty Cycle</b><br>Defines the waveform duty cycle. THis value must be defined between 0 and CPRD(PWMC_CPRx).</td></tr>
</null></table>
<a name="PWMC_CPRDR"></a><h4><a href="#PWMC_CH">PWMC_CH</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> PWMC_CPRDR  <i>Channel Period Register</i></h4><ul><null><font size="-2"><li><b>PWMC_CH3</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH3_CPRDR">AT91C_PWMC_CH3_CPRDR</a></i> 0xFFFCC268</font><font size="-2"><li><b>PWMC_CH2</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH2_CPRDR">AT91C_PWMC_CH2_CPRDR</a></i> 0xFFFCC248</font><font size="-2"><li><b>PWMC_CH1</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH1_CPRDR">AT91C_PWMC_CH1_CPRDR</a></i> 0xFFFCC228</font><font size="-2"><li><b>PWMC_CH0</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH0_CPRDR">AT91C_PWMC_CH0_CPRDR</a></i> 0xFFFCC208</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">31..0</td><td align="CENTER"><a name="PWMC_CPRD"></a><b>PWMC_CPRD</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CPRD">AT91C_PWMC_CPRD</a></font></td><td><b>Channel Period</b><br>If the waveform is left aligned, its period is CPRD*TMCK.<br>If the waveform is center aligned, its period is 2*CPRD*TMCK.</td></tr>
</null></table>
<a name="PWMC_CCNTR"></a><h4><a href="#PWMC_CH">PWMC_CH</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> PWMC_CCNTR  <i>Channel Counter Register</i></h4><ul><null><font size="-2"><li><b>PWMC_CH3</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH3_CCNTR">AT91C_PWMC_CH3_CCNTR</a></i> 0xFFFCC26C</font><font size="-2"><li><b>PWMC_CH2</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH2_CCNTR">AT91C_PWMC_CH2_CCNTR</a></i> 0xFFFCC24C</font><font size="-2"><li><b>PWMC_CH1</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH1_CCNTR">AT91C_PWMC_CH1_CCNTR</a></i> 0xFFFCC22C</font><font size="-2"><li><b>PWMC_CH0</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH0_CCNTR">AT91C_PWMC_CH0_CCNTR</a></i> 0xFFFCC20C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">31..0</td><td align="CENTER"><a name="PWMC_CCNT"></a><b>PWMC_CCNT</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CCNT">AT91C_PWMC_CCNT</a></font></td><td><b>Channel Counter</b><br>Internal Counter Value.</td></tr>
</null></table>
<a name="PWMC_CUPDR"></a><h4><a href="#PWMC_CH">PWMC_CH</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> PWMC_CUPDR  <i>Channel Update Register</i></h4><ul><null><font size="-2"><li><b>PWMC_CH3</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH3_CUPDR">AT91C_PWMC_CH3_CUPDR</a></i> 0xFFFCC270</font><font size="-2"><li><b>PWMC_CH2</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH2_CUPDR">AT91C_PWMC_CH2_CUPDR</a></i> 0xFFFCC250</font><font size="-2"><li><b>PWMC_CH1</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH1_CUPDR">AT91C_PWMC_CH1_CUPDR</a></i> 0xFFFCC230</font><font size="-2"><li><b>PWMC_CH0</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH0_CUPDR">AT91C_PWMC_CH0_CUPDR</a></i> 0xFFFCC210</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">31..0</td><td align="CENTER"><a name="PWMC_CUPD"></a><b>PWMC_CUPD</b><font size="-2"><br><a href="AT91SAM7S128_h.html#AT91C_PWMC_CUPD">AT91C_PWMC_CUPD</a></font></td><td><b>Channel Update</b><br>This register is a double buffer for the period or the duty cycle (CUP in PWMC_CMRx).<br>It prevents from unexpected waveform when modifying waveform period or duty cycle.</td></tr>
</null></table>
<a name="Reserved"></a><h4><a href="#PWMC_CH">PWMC_CH</a>: <i><a href="AT91SAM7S128_h.html#AT91_REG">AT91_REG</a></i> Reserved  <i>Reserved</i></h4><ul><null><font size="-2"><li><b>PWMC_CH3</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH3_Reserved">AT91C_PWMC_CH3_Reserved</a></i> 0xFFFCC274</font><font size="-2"><li><b>PWMC_CH2</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH2_Reserved">AT91C_PWMC_CH2_Reserved</a></i> 0xFFFCC254</font><font size="-2"><li><b>PWMC_CH1</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH1_Reserved">AT91C_PWMC_CH1_Reserved</a></i> 0xFFFCC234</font><font size="-2"><li><b>PWMC_CH0</b> <i><a href="AT91SAM7S128_h.html#AT91C_PWMC_CH0_Reserved">AT91C_PWMC_CH0_Reserved</a></i> 0xFFFCC214</font></null></ul></null><hr></html>