at91sam7s128_h.html

atmel at91sam7s和7x下

	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_DBGU.html#DBGU_EXID">DBGU_EXID</a>; 	<font color=#B22222>// Chip ID Extension Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_DBGU.html#DBGU_FNTR">DBGU_FNTR</a>; 	<font color=#B22222>// Force NTRST Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved4[45]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 DBGU_RPR; 	<font color=#B22222>// Receive Pointer Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 DBGU_RCR; 	<font color=#B22222>// Receive Counter Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 DBGU_TPR; 	<font color=#B22222>// Transmit Pointer Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 DBGU_TCR; 	<font color=#B22222>// Transmit Counter Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 DBGU_RNPR; 	<font color=#B22222>// Receive Next Pointer Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 DBGU_RNCR; 	<font color=#B22222>// Receive Next Counter Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 DBGU_TNPR; 	<font color=#B22222>// Transmit Next Pointer Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 DBGU_TNCR; 	<font color=#B22222>// Transmit Next Counter Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 DBGU_PTCR; 	<font color=#B22222>// <a href="AT91SAM7S128_PDC.html#PDC">PDC</a> Transfer Control Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 DBGU_PTSR; 	<font color=#B22222>// <a href="AT91SAM7S128_PDC.html#PDC">PDC</a> Transfer Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved5[54]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_PER; 	<font color=#B22222>// <a href="AT91SAM7S128_PIO.html#PIO">PIO</a> Enable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_PDR; 	<font color=#B22222>// <a href="AT91SAM7S128_PIO.html#PIO">PIO</a> Disable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_PSR; 	<font color=#B22222>// <a href="AT91SAM7S128_PIO.html#PIO">PIO</a> Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved6[1]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_OER; 	<font color=#B22222>// Output Enable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_ODR; 	<font color=#B22222>// Output Disable Registerr</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_OSR; 	<font color=#B22222>// Output Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved7[1]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_IFER; 	<font color=#B22222>// Input Filter Enable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_IFDR; 	<font color=#B22222>// Input Filter Disable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_IFSR; 	<font color=#B22222>// Input Filter Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved8[1]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_SODR; 	<font color=#B22222>// Set Output Data Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_CODR; 	<font color=#B22222>// Clear Output Data Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_ODSR; 	<font color=#B22222>// Output Data Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_PDSR; 	<font color=#B22222>// Pin Data Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_IER; 	<font color=#B22222>// Interrupt Enable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_IDR; 	<font color=#B22222>// Interrupt Disable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_IMR; 	<font color=#B22222>// Interrupt Mask Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_ISR; 	<font color=#B22222>// Interrupt Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_MDER; 	<font color=#B22222>// Multi-driver Enable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_MDDR; 	<font color=#B22222>// Multi-driver Disable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_MDSR; 	<font color=#B22222>// Multi-driver Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved9[1]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_PPUDR; 	<font color=#B22222>// Pull-up Disable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_PPUER; 	<font color=#B22222>// Pull-up Enable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_PPUSR; 	<font color=#B22222>// Pull-up Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved10[1]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_ASR; 	<font color=#B22222>// Select A Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_BSR; 	<font color=#B22222>// Select B Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_ABSR; 	<font color=#B22222>// AB Select Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved11[9]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_OWER; 	<font color=#B22222>// Output Write Enable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_OWDR; 	<font color=#B22222>// Output Write Disable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PIOA_OWSR; 	<font color=#B22222>// Output Write Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved12[469]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_SCER">PMC_SCER</a>; 	<font color=#B22222>// System Clock Enable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_SCDR">PMC_SCDR</a>; 	<font color=#B22222>// System Clock Disable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_SCSR">PMC_SCSR</a>; 	<font color=#B22222>// System Clock Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved13[1]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_PCER">PMC_PCER</a>; 	<font color=#B22222>// Peripheral Clock Enable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_PCDR">PMC_PCDR</a>; 	<font color=#B22222>// Peripheral Clock Disable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_PCSR">PMC_PCSR</a>; 	<font color=#B22222>// Peripheral Clock Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved14[1]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 PMC_MOR; 	<font color=#B22222>// Main Oscillator Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 PMC_MCFR; 	<font color=#B22222>// Main Clock  Frequency Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved15[1]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 PMC_PLLR; 	<font color=#B22222>// PLL Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_MCKR">PMC_MCKR</a>; 	<font color=#B22222>// Master Clock Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved16[3]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_PCKR">PMC_PCKR</a>[3]; 	<font color=#B22222>// Programmable Clock Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved17[5]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_IER">PMC_IER</a>; 	<font color=#B22222>// Interrupt Enable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_IDR">PMC_IDR</a>; 	<font color=#B22222>// Interrupt Disable Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_SR">PMC_SR</a>; 	<font color=#B22222>// Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PMC.html#PMC_IMR">PMC_IMR</a>; 	<font color=#B22222>// Interrupt Mask Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved18[36]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_RSTC.html#RSTC_RCR">RSTC_RCR</a>; 	<font color=#B22222>// Reset Control Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_RSTC.html#RSTC_RSR">RSTC_RSR</a>; 	<font color=#B22222>// Reset Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_RSTC.html#RSTC_RMR">RSTC_RMR</a>; 	<font color=#B22222>// Reset Mode Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved19[5]; 	<font color=#B22222>// </font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_RTTC.html#RTTC_RTMR">RTTC_RTMR</a>; 	<font color=#B22222>// Real-time Mode Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_RTTC.html#RTTC_RTAR">RTTC_RTAR</a>; 	<font color=#B22222>// Real-time Alarm Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_RTTC.html#RTTC_RTVR">RTTC_RTVR</a>; 	<font color=#B22222>// Real-time Value Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_RTTC.html#RTTC_RTSR">RTTC_RTSR</a>; 	<font color=#B22222>// Real-time Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PITC.html#PITC_PIMR">PITC_PIMR</a>; 	<font color=#B22222>// Period Interval Mode Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PITC.html#PITC_PISR">PITC_PISR</a>; 	<font color=#B22222>// Period Interval Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PITC.html#PITC_PIVR">PITC_PIVR</a>; 	<font color=#B22222>// Period Interval Value Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_PITC.html#PITC_PIIR">PITC_PIIR</a>; 	<font color=#B22222>// Period Interval Image Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_WDTC.html#WDTC_WDCR">WDTC_WDCR</a>; 	<font color=#B22222>// Watchdog Control Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_WDTC.html#WDTC_WDMR">WDTC_WDMR</a>; 	<font color=#B22222>// Watchdog Mode Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 <a href="AT91SAM7S128_WDTC.html#WDTC_WDSR">WDTC_WDSR</a>; 	<font color=#B22222>// Watchdog Status Register</font>
	<a href="#AT91_REG">AT91_REG</a>	 Reserved20[5]; 	<font color=#B22222>// </font>