📄 l2.lst
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001:000263 0000004C F4050000 =00000000 cabaccess w0, #cabwrite 001:000264 0000004D A4000000 nop 001:000265 0000004E E0000020 =00000020 WAIT COP_CAB 001:000267 0000004F B1743FFF =00003FFF ldr r8, #0x3FFF001:000268 00000050 B074FC00 =0000FC00 ldr r9, #0xFC00001:000269 00000051 76744401 str cabdata, w8001:000270 00000052 80700001 =00000001 add r1, #1 ; DMU cfg C word 2001:000271 00000053 F4050000 =00000000 cabaccess w0, #cabwrite001:000272 00000054 A4000000 nop001:000273 00000055 E0000020 =00000020 WAIT COP_CAB 001:000275 00000056 B2740000 =00000000 ldrh w8, #0x00001:000276 00000057 76744401 str cabdata, w8 001:000277 00000058 80700001 =00000001 add r1, #1 ; DMU cfg C word 3001:000278 00000059 F4050000 =00000000 cabaccess w0, #cabwrite 001:000279 0000005A A4000000 nop 001:000280 0000005B E0000020 =00000020 WAIT COP_CAB ;************************************************************** ; Init DMU D ; Tx Thresh = 2, 10/100 SMII , Tx enable all, Rx enable all, FDX all ;**************************************************************001:000286 0000005C B0700080 =00000080 ldr r1, #DMU_D_Cnfg_Reg_Lo_Addr ; Word 0 not written 001:000288 0000005D B1740043 =00000043 ldr r8, #0x0043 ; Reset value001:000289 0000005E B07407FF =000007FF ldr r9, #0x07FF001:000290 0000005F 76744401 str cabdata, w8 001:000291 00000060 80700001 =00000001 add r1,#1 ; DMU cfg D word 1 001:000292 00000061 F4050000 =00000000 cabaccess w0, #cabwrite 001:000293 00000062 A4000000 nop 001:000294 00000063 E0000020 =00000020 WAIT COP_CAB 001:000296 00000064 B1743FFF =00003FFF ldr r8, #0x3FFF001:000297 00000065 B074FC00 =0000FC00 ldr r9, #0xFC00001:000298 00000066 76744401 str cabdata, w8001:000299 00000067 80700001 =00000001 add r1, #1 ; DMU cfg D word 2001:000300 00000068 F4050000 =00000000 cabaccess w0, #cabwrite001:000301 00000069 A4000000 nop001:000302 0000006A E0000020 =00000020 WAIT COP_CAB 001:000304 0000006B B2740000 =00000000 ldrh w8, #0x00001:000305 0000006C 76744401 str cabdata, w8 001:000306 0000006D 80700001 =00000001 add r1, #1 ; DMU cfg C word 3001:000307 0000006E F4050000 =00000000 cabaccess w0, #cabwrite 001:000308 0000006F A4000000 nop 001:000309 00000070 E0000020 =00000020 WAIT COP_CAB 17 Nov 2005 15:42:05 l2.asm Page 6File:Line Address OpCode Ref. Value Source Code v3.2.0========== ======== ======== ========== = ================================================================================ ;************************************************************** ; DMU's should be configured ; Poll DMU reset bit to wait for all enables ;**************************************************************001:000315 00000071 B170A001 =0000A001 ldr r0, #DMU_Cnfg_Reg_Hi_Addr ; all dmu cnfg regs hi addr 001:000317 00000072 B0700010 =00000010 dmu_a ldr r1, #DMU_A_Cnfg_Reg_Lo_Addr001:000318 00000073 F4050001 =00000001 cabaccess w0, #cabread001:000319 00000074 66714401 ldr w2,cabdata001:000320 00000075 B0718000 =00008000 ldr r3, #0x8000001:000321 00000076 C1711504 and r2, r3 ;; Mask off all but high bit001:000322 00000077 A1710000 =00000000 cmp r2, #0x0000 ;; Make sure reset is off001:000323 00000078 1A10FFF9 =00000072 bne dmu_a 001:000325 00000079 B0700020 =00000020 dmu_b ldr r1, #DMU_B_Cnfg_Reg_Lo_Addr001:000326 0000007A F4050001 =00000001 cabaccess w0, #cabread001:000327 0000007B 66714401 ldr w2,cabdata001:000328 0000007C B0718000 =00008000 ldr r3, #0x8000001:000329 0000007D C1711504 and r2, r3 ;; Mask off all but high bit001:000330 0000007E A1710000 =00000000 cmp r2, #0x0000 ;; Make sure reset is off001:000331 0000007F 1A10FFF9 =00000079 bne dmu_b 001:000333 00000080 B0700040 =00000040 dmu_c ldr r1, #DMU_C_Cnfg_Reg_Lo_Addr001:000334 00000081 F4050001 =00000001 cabaccess w0, #cabread001:000335 00000082 66714401 ldr w2,cabdata001:000336 00000083 B0718000 =00008000 ldr r3, #0x8000001:000337 00000084 C1711504 and r2, r3 ;; Mask off all but high bit001:000338 00000085 A1710000 =00000000 cmp r2, #0x0000 ;; Make sure reset is off001:000339 00000086 1A10FFF9 =00000080 bne dmu_c 001:000341 00000087 B0700080 =00000080 dmu_d ldr r1, #DMU_D_Cnfg_Reg_Lo_Addr001:000342 00000088 F4050001 =00000001 cabaccess w0, #cabread001:000343 00000089 66714401 ldr w2,cabdata001:000344 0000008A B0718000 =00008000 ldr r3, #0x8000001:000345 0000008B C1711504 and r2, r3 ;; Mask off all but high bit001:000346 0000008C A1710000 =00000000 cmp r2, #0x0000 ;; Make sure reset is off001:000347 0000008D 1A10FFF9 =00000087 bne dmu_d ;************************************************************** ; Start the dmu h/w initialization by setting ; the DMU init bit in the init register ; rather than reading and or'ing the SIF and Island Bits back in ; I'm just setting them again ;**************************************************************001:000356 0000008E B674FC00 =0000FC00 ldru w8, #0xFC00 ; r8 = 0xFC00, r9 = 0001:000357 0000008F 76744401 str cabdata , w8 001:000359 00000090 B170A000 =0000A000 ldr r0, #Init_Reg_Hi_Addr001:000360 00000091 B0708100 =00008100 ldr r1, #Init_Reg_Lo_Addr001:000361 00000092 F4050000 =00000000 cabaccess w0, #cabwrite ;************************************************************** ; Poll init done register till all the bits are set to ; '1' indicating the island initialization completion. ;************************************************************** =00000093 poll_init_done_again2 EQU $001:000368 00000093 B170A000 =0000A000 ldr r0, #Init_Done_Reg_Hi_Addr001:000369 00000094 B0708200 =00008200 ldr r1, #Init_Done_Reg_Lo_Addr001:000370 00000095 F4050001 =00000001 cabaccess w0, #cabread001:000371 00000096 66714401 ldr w2,cabdata001:000372 00000097 B071FFFF =0000FFFF ldr r3, #0xFFFF 17 Nov 2005 15:42:05 l2.asm Page 7File:Line Address OpCode Ref. Value Source Code v3.2.0========== ======== ======== ========== = ================================================================================001:000373 00000098 C1711504 and r2, r3 ; Check only the relevant bits.001:000374 00000099 C1711B04 cmp r2, r3001:000375 0000009A 1A000000 =???????? be TP_data_store_map001:000376 0000009B 1A70FFF7 =00000093 b poll_init_done_again2 ;************************************************************** ; Set up Target Port Data Store Map(TP_DS_MAP) Register ; DMU C & D = DS1 ; DMC A & B = DS0 ;************************************************************** =0000009C TP_data_store_map EQU $ 001:000384 0000009C B170A000 =0000A000 ldr r0, #Tp_DS_Map_Reg_Hi_Addr ; same hi addr for all writes001:000385 0000009D B174AAAA =0000AAAA ldr r8, #0xAAAA 001:000386 0000009E B074AAAA =0000AAAA ldr r9, #0xAAAA 001:000387 0000009F 76744401 str cabdata, w8 001:000388 000000A0 B0700140 =00000140 ldr r1, #Tp_DS_Map_Reg_Lo_Addr001:000389 000000A1 F4050000 =00000000 cabaccess w0, #cabwrite 001:000390 000000A2 A4000000 nop 001:000391 000000A3 E0000020 =00000020 WAIT COP_CAB 001:000393 000000A4 B174AA55 =0000AA55 ldr r8, #0xAA55 001:000394 000000A5 B0745555 =00005555 ldr r9, #0x5555 001:000395 000000A6 76744401 str cabdata, w8 ⌨️ 快捷键说明
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