📄 l2.lst
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; *************** ; None ; ;**********************************************************************; =00000000 NP_Boot EQU $001:000135 00000000 F4000001 =00000001 cabarb #cabrequest ;; Arbitrate for the CAB ;************************************************************** ; Configure the NP Memories ;**************************************************************001:000140 00000001 B1740000 =00000000 ldr r8, #0x0000001:000141 00000002 B07403F7 =000003F7 ldr r9, #0x03F7 ; All Memories001:000142 00000003 76744401 str cabdata, w8001:000143 00000004 B170A000 =0000A000 ldr r0,#Mem_Cnfg_Reg_Hi_Addr 001:000144 00000005 B0700120 =00000120 ldr r1,#Mem_Cnfg_Reg_Lo_Addr 001:000145 00000006 F4050000 =00000000 cabaccess w0, #cabwrite001:000146 00000007 A4000000 nop001:000147 00000008 E0000020 =00000020 WAIT COP_CAB ;************************************************************** ; DRAM Controller Initialization ; Start the internal h/w initialization by setting ; the dram init & island init bits in the init register ;**************************************************************001:000154 00000009 B6740400 =00000400 ldru w8, #0x0400 ; DRAM init- r8 = 0x0400, r9 = 0001:000155 0000000A 76744401 str cabdata , w8001:000156 0000000B B170A000 =0000A000 ldr r0,#Init_Reg_Hi_Addr001:000157 0000000C B0708100 =00008100 ldr r1,#Init_Reg_Lo_Addr001:000158 0000000D F4050000 =00000000 cabaccess w0, #cabwrite ;************************************************************** ; Poll init done register till both DRAM bits are set to ; '1' indicating the DRAM init completion. ;************************************************************** =0000000E poll_init_done_again1 EQU $ 001:000166 0000000E B170A000 =0000A000 ldr r0, #Init_Done_Reg_Hi_Addr001:000167 0000000F B0708200 =00008200 ldr r1, #Init_Done_Reg_Lo_Addr001:000168 00000010 F4050001 =00000001 cabaccess w0, #cabread001:000169 00000011 66714401 ldr w2, cabdata001:000170 00000012 B0710030 =00000030 ldr r3, #DDS_CM_Init_Done_Mask001:000171 00000013 C1711504 and r2, r3 ; Check only the relevant bits.001:000172 00000014 C1711B04 cmp r2, r3 ; Check DRAMs001:000173 00000015 1A000000 =???????? be initb001:000174 00000016 1A70FFF7 =0000000E b poll_init_done_again1 ;************************************************************** ; Turn on the SIF and Island inits, wait on the DMU's ;************************************************************** =00000017 initb EQU $001:000180 00000017 B6740C00 =00000C00 ldru w8, #0x0C00 ; r8 = 0x0C00, r9 = 0001:000181 00000018 76744401 str cabdata , w8 001:000183 00000019 B170A000 =0000A000 ldr r0,#Init_Reg_Hi_Addr001:000184 0000001A B0708100 =00008100 ldr r1,#Init_Reg_Lo_Addr001:000185 0000001B F4050000 =00000000 cabaccess w0, #cabwrite 17 Nov 2005 15:42:05 l2.asm Page 4File:Line Address OpCode Ref. Value Source Code v3.2.0========== ======== ======== ========== = ================================================================================ ;************************************************************** ; DMU Config and Init ; Configure the DMU's before starting initialization on DMU's ; Program all the Phy DMU CONFIG registers ;************************************************************** 001:000193 0000001C B170A001 =0000A001 ldr r0, #DMU_Cnfg_Reg_Hi_Addr ; all dmu cnfg regs hi addr ;************************************************************** ; Init DMU A ; Tx Thresh = 2, 10/100 SMII , Tx enable all, Rx enable all,FDX all ;**************************************************************001:000199 0000001D B0700010 =00000010 ldr r1, #DMU_A_Cnfg_Reg_Lo_Addr ; DMU cfg A word 0 not written 001:000201 0000001E B1740043 =00000043 ldr r8, #0x0043 ; Reset value001:000202 0000001F B07407FF =000007FF ldr r9, #0x07FF001:000203 00000020 76744401 str cabdata, w8 001:000204 00000021 80700001 =00000001 add r1, #1 ; DMU cfg A word 1 001:000205 00000022 F4050000 =00000000 cabaccess w0, #cabwrite 001:000206 00000023 A4000000 nop 001:000207 00000024 E0000020 =00000020 WAIT COP_CAB 001:000209 00000025 B1743FFF =00003FFF ldr r8, #0x3FFF001:000210 00000026 B074FC00 =0000FC00 ldr r9, #0xFC00001:000211 00000027 76744401 str cabdata, w8001:000212 00000028 80700001 =00000001 add r1, #1 ; DMU cfg A word 2001:000213 00000029 F4050000 =00000000 cabaccess w0, #cabwrite001:000214 0000002A A4000000 nop001:000215 0000002B E0000020 =00000020 WAIT COP_CAB 001:000217 0000002C B2740000 =00000000 ldrh w8, #0x00001:000218 0000002D 76744401 str cabdata, w8 001:000219 0000002E 80700001 =00000001 add r1, #1 ; DMU cfg A word 3001:000220 0000002F F4050000 =00000000 cabaccess w0, #cabwrite 001:000221 00000030 A4000000 nop 001:000222 00000031 E0000020 =00000020 WAIT COP_CAB ;************************************************************** ; Init DMU B ; Tx Thresh = 2, 10/100 SMII , Tx enable all, Rx enable all, FDX all ;**************************************************************001:000228 00000032 B0700020 =00000020 ldr r1, #DMU_B_Cnfg_Reg_Lo_Addr ; DMU cfg B word 0 not written 001:000230 00000033 B1740043 =00000043 ldr r8, #0x0043 ; Reset value001:000231 00000034 B07407FF =000007FF ldr r9, #0x07FF001:000232 00000035 76744401 str cabdata, w8 001:000233 00000036 80700001 =00000001 add r1,#1 ; DMU cfg B word 1 001:000234 00000037 F4050000 =00000000 cabaccess w0, #cabwrite 001:000235 00000038 A4000000 nop 001:000236 00000039 E0000020 =00000020 WAIT COP_CAB 001:000238 0000003A B1743FFF =00003FFF ldr r8, #0x3FFF001:000239 0000003B B074FC00 =0000FC00 ldr r9, #0xFC00001:000240 0000003C 76744401 str cabdata, w8001:000241 0000003D 80700001 =00000001 add r1, #1 ; DMU cfg B word 2001:000242 0000003E F4050000 =00000000 cabaccess w0, #cabwrite001:000243 0000003F A4000000 nop001:000244 00000040 E0000020 =00000020 WAIT COP_CAB 001:000246 00000041 B2740000 =00000000 ldrh w8, #0x00001:000247 00000042 76744401 str cabdata, w8 001:000248 00000043 80700001 =00000001 add r1, #1 ; DMU cfg B word 3 17 Nov 2005 15:42:05 l2.asm Page 5File:Line Address OpCode Ref. Value Source Code v3.2.0========== ======== ======== ========== = ================================================================================001:000249 00000044 F4050000 =00000000 cabaccess w0, #cabwrite 001:000250 00000045 A4000000 nop 001:000251 00000046 E0000020 =00000020 WAIT COP_CAB ;************************************************************** ; Init DMU C ; Tx Thresh = 2, 10/100 SMII , Tx enable all, Rx enable all, FDX all ;**************************************************************001:000257 00000047 B0700040 =00000040 ldr r1, #DMU_C_Cnfg_Reg_Lo_Addr ; Word 0 not written 001:000259 00000048 B1740043 =00000043 ldr r8, #0x0043 ; Reset value001:000260 00000049 B07407FF =000007FF ldr r9, #0x07FF001:000261 0000004A 76744401 str cabdata, w8 001:000262 0000004B 80700001 =00000001 add r1,#1 ; DMU cfg C word 1 ⌨️ 快捷键说明
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