📄 l2.inc
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; *************; CAB Addresses; ************* Mem_Cnfg_Reg_Hi_Addr EQU 0xA000 ; Memory Config Reg CAB Addr HiMem_Cnfg_Reg_Lo_Addr EQU 0x0120 ; Memory Config Reg CAB Addr Lo FQ_ES_Max_Hi_Addr EQU 0xA000 ; Free Queue Ext. Stack Max Size Addr HiFQ_ES_Max_Lo_Addr EQU 0x2100 ; Free Queue Ext. Stack Max Size Addr LoInit_Reg_Hi_Addr EQU 0xA000 ; Init Register CAB Address HiInit_Reg_Lo_Addr EQU 0x8100 ; Init Register CAB Address LoInit_Done_Reg_Hi_Addr EQU 0xA000 ; Init Done Register CAB Addr HiInit_Done_Reg_Lo_Addr EQU 0x8200 ; Init Done Register CAB Addr LoDASL_Start_Reg_Hi_Addr EQU 0xA000 ; DASL Start Register CAB Addr HiDASL_Start_Reg_Lo_Addr EQU 0x0210 ; DASL Start Register CAB Addr LoDASL_Config_Reg_Hi_Addr EQU 0xA000 ; DASL Config Register CAB Addr HiDASL_Config_Reg_Lo_Addr EQU 0x0110 ; DASL Config Register CAB Addr LoDMU_Cnfg_Reg_Hi_Addr EQU 0xA001 ; DMU Config Reg. Word 0 CAB Addr HiDMU_A_Cnfg_Reg_Lo_Addr EQU 0x0010 ; DMU A Config Reg. Word 0 CAB Addr LoDMU_B_Cnfg_Reg_Lo_Addr EQU 0x0020 ; DMU B Config Reg. Word 0 CAB Addr Lo DMU_C_Cnfg_Reg_Lo_Addr EQU 0x0040 ; DMU C Config Reg. Word 0 CAB Addr LoDMU_D_Cnfg_Reg_Lo_Addr EQU 0x0080 ; DMU D Config Reg. Word 0 CAB Addr LoUp_TP_DSU_Reg_Hi_Addr EQU 0xA000 ; Up TP DS Reg. CAB Addr HiUp_TP_DSU_Reg_Lo_Addr EQU 0x0180 ; Up TP DS Reg. CAB Addr LoTp_DS_Map_Reg_Hi_Addr EQU 0xA000 ; Tp DS Map Reg. CAB Addr HiTp_DS_Map_Reg_Lo_Addr EQU 0x0140 ; Tp DS Map Reg. CAB Addr LoE_Type_C_Reg_Hi_Addr EQU 0xA001 ; E Type C Reg. CAB Addr HiE_Type_C_Reg_Lo_Addr EQU 0x1000 ; E Type C Reg. CAB Addr LoCLP_Enable_Reg_Hi_Addr EQU 0xA000 ; CLP Enable Register CAB Addr HiCLP_Enable_Reg_Lo_Addr EQU 0x8020 ; CLP Enable Register CAB Addr LoNP_Rdy_Hi_Addr EQU 0xA004 ; NP Ready Register CAB Addr HiNP_Rdy_Lo_Addr EQU 0x0020 ; NP Ready Register CAB Addr LoE_SDM_Stack_TH_Hi_Addr EQU 0xA000 ; Down Switch Data Mover Thresh Hi AddrE_SDM_Stack_TH_Lo_Addr EQU 0x1800 ; Down Switch Data Mover Thresh Lo AddrLocal_TB_Vec_Reg_Hi_Addr EQU 0xA000 ; Local Target Blade Vector HiLocal_TB_Vec_Reg_Lo_Addr EQU 0x4100 ; Local Target Blade Vector LoBCB_FQ_Threshold_Hi_Addr EQU 0xA000 ; Buffer Control Block threshold gcBCB_FQ_Threshold_GC_Lo_Addr EQU 0x1080 ; Buffer Control Block threshold gcBCB_FQ_Threshold_0_Lo_Addr EQU 0x1010 ; Buffer Control Block threshold 0BCB_FQ_Threshold_1_Lo_Addr EQU 0x1020 ; Buffer Control Block threshold 1BCB_FQ_Threshold_2_Lo_Addr EQU 0x1040 ; Buffer Control Block threshold 2FQ_ES_TH_Hi_Addr EQU 0xA000 ; Free queue extended stack thresh 0FQ_ES_TH0_Lo_Addr EQU 0x2010 ; Free queue extended stack thresh 0FQ_ES_TH1_Lo_Addr EQU 0x2020 ; Free queue extended stack thresh 1FQ_ES_TH2_Lo_Addr EQU 0x2040 ; Free queue extended stack thresh 2Probe_Ctrl_Hi_Addr EQU 0xA008 ; Probe Control Hi Addr Probe_Master_Ctrl_Lo_Addr EQU 0x0020 ; Probe Master Control lo addr Probe_RPC_Ctrl_Lo_Addr EQU 0x0400 ; Probe RPC control lo addr Timer_Target_Reg_Hi_Addr EQU 0x2440 Timer_Target_Reg0_Lo_Addr EQU 0x0440 Timer_Target_Reg1_Lo_Addr EQU 0x0450 Timer_Target_Reg2_Lo_Addr EQU 0x0460 Timer_Target_Reg3_Lo_Addr EQU 0x0470 Int_Target_Reg_Hi_Addr EQU 0x2440 ; Interrupt Target Register Int_Target_Reg0_Lo_Addr EQU 0x0800 ; Interrupt Target Register Int_Target_Reg1_Lo_Addr EQU 0x0810 ; Interrupt Target Register Int_Target_Reg2_Lo_Addr EQU 0x0820 ; Interrupt Target Register Int_Target_Reg3_Lo_Addr EQU 0x0830 ; Interrupt Target Register My_Target_Blade_Hi_Addr EQU 0xA000 ; My Target Blade Addr Hi My_Target_Blade_Lo_Addr EQU 0x4080 ; My Target Blade Addr Lo Int_Mask_Hi_Addr EQU 0x24C0 ; Interrupt Mask Addr Hi Int_Mask_0_Lo_Addr EQU 0x0080 ; Interrupt Mask 0 Addr Lo Int_Mask_1_Lo_Addr EQU 0x0090 ; Interrupt Mask 1 Addr Lo Int_Mask_2_Lo_Addr EQU 0x00A0 ; Interrupt Mask 2 Addr Lo Int_Mask_3_Lo_Addr EQU 0x00B0 ; Interrupt Mask 3 Addr Lo Int_Vector_Hi_Addr EQU 0x24C0 ; Interrupt Vector Addr Hi Int_Vector_0_Lo_Addr EQU 0x0100 ; Interrupt Vector 0 Addr Lo Int_Vector_1_Lo_Addr EQU 0x0110 ; Interrupt Vector 1 Addr Lo Int_Vector_2_Lo_Addr EQU 0x0120 ; Interrupt Vector 2 Addr Lo Int_Vector_3_Lo_Addr EQU 0x0130 ; Interrupt Vector 3 Addr Lo Unexpected_disp_Log_hi_addr EQU 0x0230 ; address of the unexpected dispatch logUnexpected_disp_Log_lo_addr EQU 0x0003 ; address of the unexpected dispatch logdispatch_cfg_hi_addr EQU 0x2440 ; dispatch port cfg structure hi addr ; this is the hi addr for the dispatch ; addressesdispatch_port0_cfg_lo_addr EQU 0x0000 ; dispatch port0 cfg structure lo addr dispatch_DN_F_UC_lo_addr EQU 0x0300 ; dispatch port config for dn unicast addr dispatch_DN_F_MC_lo_addr EQU 0x0310 ; dispatch port config for dn multicast addr dispatch_UP_GCH_lo_addr EQU 0x02A0 ; dispatch port config for UP GCH dispatch_UP_Wrap_G_lo_addr EQU 0x02B0 ; dispatch port config of Up wrap Guided dispatch_GPQ_lo_addr EQU 0x02D0 ; dispatch port config of GPQdispatch_DN_GCH_lo_addr EQU 0x02E0 ; dispatch port config for dn GCH addr dispatch_UP_Wrap_D_lo_addr EQU 0x0280 ; dispatch port config for up wrap data dispatch_Dn_Abort_lo_addr EQU 0x0360 ; dispatch port config for Dn abort dispatch_Dn_GTH_lo_addr EQU 0x02F0 ; dispatch port config for reserved41 dispatch_Res41_lo_addr EQU 0x0290 ; dispatch port config for Up GTH dispatch_Int0_lo_addr EQU 0x0380 ; dispatch port config for level 0 int dispatch_Timer0_lo_addr EQU 0x03C0 ; dispatch port config for level 0 timer dispatch_Res50_lo_addr EQU 0x0320 ; dispatch port config for reserved54 dispatch_Res44_lo_addr EQU 0x02C0 ; dispatch port config for reserved40 up_pcb_ctrl_block_hi_addr EQU 0x1001 ; up port control blocks hi addrup_pcb_ctrl_block_lo_addr EQU 0x0000 ; up port control blocks lo addrup_pcb_ctrl_block_end_addr EQU 0x0270 ; up port control blocks end lo addr;; end CAB Addresses;; CABARB argumentsCABRequest EQU 1CABRelease EQU 0CABRead EQU 1CABWrite EQU 0COP_CAB EQU 0x0020COP_TSE0 EQU 0x0004; ENQUP instruction argument definitonsUp_DiscardQ EQU 0Up_TXQ EQU 5; ENQDN instruction argument definitonsDn_PortQ EQU 1;; miscellaneous masksDDS_CM_Init_Done_Mask EQU 0x0030 ; Ctrl_Mem and D_DS Initialized Mask;; guided frame masksgf_rq_rsp_mask equ 0x0080 ; mask to isolate rq/rsp bitgf_rw_mask equ 0x000C ; mask to isolate R/W in cmd typegf_rw equ 0x0004 ; R/W commandsgf_read_mask equ 0x0002 ; mask to isolate Read commandgf_isl_id_mask equ 0xF800 ; mask to isolate island idgf_ctrl_mem_id equ 0x4000 ; control mem island idgf_leaf_mask equ 0x0008 ; mask to isolate leaf in cmd typegf_other_mask equ 0x0003 ; mask to isolate other cmdsgf_end_del equ 0x0000 ; end del commandgf_free_list equ 0x0001 ; build free list commandgf_unsolicited equ 0x0003 ; unsolicited command;; end MasksDA_Lookup_parms_tsr0 EQU (42 << 5 | (TSEDPA_TSR0 << 1) | LCBAN0);LID_Lookup_parms_tsr0 EQU (43 << 5 | (TSEDPA_TSR0 << 1) | LCBAN0);l2_FFAC_START_BYTE EQU (7*16); ; start of frame in frame alteration area;======================================================= ;; 4gs3 ; bci field in egress fcb page ;; 4gs3 ;======================================================= ;; 4gs3 RECORD BCI_ { rsvd : 12 ; reserved start_byte : 6 ; starting byte numbuffers : 8 ; number of data buffers end_byte : 6 ; ending byte} ;======================================================= ;; 4gs3 ; twin link fields for egress data store ;; 4gs3 ;======================================================= ;; 4gs3 RECORD twin_link { ;; 4gs3 link_pointer : 19 ; pointer to next buffer ;; 4gs3 rsvd1 : 3 ; parity and reserved bits ;; 4gs3 twinQHD : 1 ; =1, next buffer is a header twin ;; 4gs3 QSBv : 1 ; =1, QSB field is valid ;; 4gs3 rsvd2 : 1 ; reserved ;; 4gs3 QSB : 7 ; starting byte of data in next twin ;; 4gs3 } ⌨️ 快捷键说明
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