spi_mcbsp.c

ti_dsp_6000系列,开发环境ccs3.1 文件内容,与spi_rom的连接,用串口实现spi协议

        EDMA_OPT_ATCINT_DEFAULT,
        EDMA_OPT_ATCC_DEFAULT,
        EDMA_OPT_PDTS_DEFAULT,
        EDMA_OPT_PDTD_DEFAULT,
        EDMA_OPT_LINK_YES,       /* Enable linking to NULL table            */
        EDMA_OPT_FS_NO

        ),
#endif        
        EDMA_SRC_RMK((Uint32)edmaOutbuff), /*src to edmaOutbuff        */
        EDMA_CNT_RMK(0,xfer_size),  /* set count equal to xfer_size    */
        EDMA_DST_RMK(MCBSP_ADDRH(hMcbsp0, DXR)), /* dst addr to DXR0   */
        EDMA_IDX_RMK(0,0),
        EDMA_RLD_RMK(0,0)
        );

  hEdmadummy = EDMA_allocTable(-1); /* Dynamically allocates PaRAM RAM table*/
  EDMA_configArgs(hEdmadummy, /* Dummy or Terminating Table in PaRAM        */
         0x00000000,          /* Terminate EDMA transfers by linking to     */     
         0x00000000,          /* this NULL table                            */
         0x00000000,         
         0x00000000,  
         0x00000000,        
         0x00000000
         );

  EDMA_link(hEdma1, hEdmadummy); /* Link terminating event to the EDMA event */
  EDMA_link(hEdma2, hEdmadummy);

  EDMA_enableChannel(hEdma1);    /* Enable EDMA channels */
  EDMA_enableChannel(hEdma2);

  #endif  /* end for EDMA supporting devices             */  
  } 

MCBSP_enableRcv(hMcbsp0); /* Enable McBSP channel                     */
MCBSP_enableXmt(hMcbsp0); /* McBSP port 0 as the transmitter/receiver */

/* To flag an interrupt to the CPU when DMA transfer/receive is done  */
#if (DMA_SUPPORT)
  while (!xmit0_done || !recv0_done);
#endif

/* To flag an interrupt to the CPU when EDMA transfer/receive is done */
/* Transfer completion interrupt 12 and 15 set flag = 1 when set      */
#if (EDMA_SUPPORT)
while (!xmit0_done || !recv0_done);
#endif

MCBSP_close(hMcbsp0);  /* close McBSP port   */

#if (DMA_SUPPORT)      /* close DMA channels */
DMA_close(hDma1);
DMA_close(hDma2);
#endif

#if (EDMA_SUPPPORT)
EDMA_close(hEdma1);    /* close EDMA channels */
EDMA_close(hEdma2);
EDMA_close(hEdmadummy);
#endif
} /* end main */

/*--------------------------------------------------------------------------------*/
/* init_mcbsp0_master()                                                           */
/*--------------------------------------------------------------------------------*/
/* MCBSP Config structure */
/* Setup the MCBSP_0 as a master */
void
init_mcbsp0_master(void)
{  
MCBSP_Config mcbspCfg0 = {  /* SPI mode, CLKSTP = 11b and CLKXP = 0: Clock  */
#if (EDMA_SUPPORT)          /* starts with rising edge with delay.          */ 
    MCBSP_SPCR_RMK(
           MCBSP_SPCR_FREE_DEFAULT,
           MCBSP_SPCR_SOFT_DEFAULT,
           MCBSP_SPCR_FRST_DEFAULT,
           MCBSP_SPCR_GRST_DEFAULT,
           MCBSP_SPCR_XINTM_DEFAULT,
           MCBSP_SPCR_XSYNCERR_DEFAULT,
           MCBSP_SPCR_XRST_DEFAULT,
           MCBSP_SPCR_DLB_DEFAULT,
           MCBSP_SPCR_RJUST_DEFAULT,
           MCBSP_SPCR_CLKSTP_DELAY, /* CLKSTP=11b with CLKXP=0, clock starts with */
           MCBSP_SPCR_DXENA_OFF,    /* rising edge with delay                     */
           MCBSP_SPCR_RINTM_DEFAULT,
           MCBSP_SPCR_RSYNCERR_DEFAULT,
           MCBSP_SPCR_RRST_DEFAULT
           ),
#endif
#if (DMA_SUPPORT)
   MCBSP_SPCR_RMK(  
          MCBSP_SPCR_FRST_DEFAULT,
          MCBSP_SPCR_GRST_DEFAULT,
          MCBSP_SPCR_XINTM_DEFAULT,
          MCBSP_SPCR_XSYNCERR_DEFAULT,
          MCBSP_SPCR_XRST_DEFAULT,
          MCBSP_SPCR_DLB_DEFAULT,
          MCBSP_SPCR_RJUST_DEFAULT,
          MCBSP_SPCR_CLKSTP_DELAY, /* CLKSTP=11b with CLKXP=0, clock starts with */
          MCBSP_SPCR_RINTM_RRDY,   /* rising edge with delay                     */
          MCBSP_SPCR_RSYNCERR_DEFAULT,
          MCBSP_SPCR_RRST_DEFAULT
          ),
#endif
#if (EDMA_SUPPORT)
    MCBSP_RCR_RMK(
           MCBSP_RCR_RPHASE_SINGLE,
           MCBSP_RCR_RFRLEN2_DEFAULT,
           MCBSP_RCR_RWDLEN2_DEFAULT,
           MCBSP_RCR_RCOMPAND_DEFAULT,
           MCBSP_RCR_RFIG_NO,
           MCBSP_RCR_RDATDLY_DEFAULT,
           MCBSP_RCR_RFRLEN1_DEFAULT,
           MCBSP_RCR_RWDLEN1_32BIT,  /* receive element length phase 1 is 32 bits */
           MCBSP_RCR_RWDREVRS_DISABLE
           ),
#endif
#if (DMA_SUPPORT)
    MCBSP_RCR_RMK(
           MCBSP_RCR_RPHASE_SINGLE,
           MCBSP_RCR_RFRLEN2_DEFAULT,
           MCBSP_RCR_RWDLEN2_DEFAULT,
           MCBSP_RCR_RCOMPAND_DEFAULT,
           MCBSP_RCR_RFIG_NO,
           MCBSP_RCR_RDATDLY_DEFAULT,
           MCBSP_RCR_RFRLEN1_DEFAULT,
           MCBSP_RCR_RWDLEN1_32BIT   /* receive element length phase 1 is 32 bits */
           ),
#endif
#if (EDMA_SUPPORT)
    MCBSP_XCR_RMK(
           MCBSP_XCR_XPHASE_DEFAULT,
           MCBSP_XCR_XFRLEN2_DEFAULT,
           MCBSP_XCR_XWDLEN2_DEFAULT,
           MCBSP_XCR_XCOMPAND_DEFAULT,
           MCBSP_XCR_XFIG_DEFAULT,
           MCBSP_XCR_XDATDLY_1BIT,    /* 1 bit data delay                    */
           MCBSP_XCR_XFRLEN1_DEFAULT,
           MCBSP_XCR_XWDLEN1_32BIT,   /* transmit element phase 1 is 32 bits */
           MCBSP_XCR_XWDREVRS_DISABLE
           ),
#endif
#if (DMA_SUPPORT)
    MCBSP_XCR_RMK(
           MCBSP_XCR_XPHASE_DEFAULT,
           MCBSP_XCR_XFRLEN2_DEFAULT,
           MCBSP_XCR_XWDLEN2_DEFAULT,
           MCBSP_XCR_XCOMPAND_DEFAULT,
           MCBSP_XCR_XFIG_DEFAULT,
           MCBSP_XCR_XDATDLY_1BIT,    /* 1 bit data delay                    */
           MCBSP_XCR_XFRLEN1_DEFAULT,
           MCBSP_XCR_XWDLEN1_32BIT    /* transmit element phase 1 is 32 bits */
           ),
#endif
     MCBSP_SRGR_RMK(
           MCBSP_SRGR_GSYNC_FREE,
           MCBSP_SRGR_CLKSP_RISING,
           MCBSP_SRGR_CLKSM_INTERNAL, /* SRGR clock mode from internal source */
           MCBSP_SRGR_FSGM_DEFAULT,
           MCBSP_SRGR_FPER_DEFAULT,
           MCBSP_SRGR_FWID_DEFAULT,
           MCBSP_SRGR_CLKGDV_OF(0x5F) /* divide clock by factor of 95         */
           ),

#if (C64_SUPPORT)
     MCBSP_MCR_RMK(                  /* only for 64x                               */
           MCBSP_MCR_XMCME_DEFAULT,  /* All fields in MCR set to default values    */
           MCBSP_MCR_XPBBLK_DEFAULT,
           MCBSP_MCR_XPABLK_DEFAULT,
           MCBSP_MCR_XMCM_DEFAULT,
           MCBSP_MCR_RPBBLK_DEFAULT,
           MCBSP_MCR_RMCME_DEFAULT,
           MCBSP_MCR_RPABLK_DEFAULT,
           MCBSP_MCR_RMCM_DEFAULT
           ),
#else
     MCBSP_MCR_RMK(
           MCBSP_MCR_XPBBLK_DEFAULT, /* All fields in MCR set to default values    */
           MCBSP_MCR_XPABLK_DEFAULT,
           MCBSP_MCR_XMCM_DEFAULT,
           MCBSP_MCR_RPBBLK_DEFAULT,
           MCBSP_MCR_RPABLK_DEFAULT,
           MCBSP_MCR_RMCM_DEFAULT
           ),
#endif
#if(!C64_SUPPORT)
     MCBSP_RCER_RMK(
           MCBSP_RCER_RCEB_DEFAULT,  /* All fields in RCER set to default values */
           MCBSP_RCER_RCEA_DEFAULT
           ),
#endif           
#if(!C64_SUPPORT)
     MCBSP_XCER_RMK(
           MCBSP_XCER_XCEB_DEFAULT,  /* All fields in XCER set to default values */
           MCBSP_XCER_XCEA_DEFAULT
           ),
#endif           

#if (C64_SUPPORT)                 
           MCBSP_RCERE0_RMK(0),      /* Additional registers only for 64x        */
           MCBSP_RCERE1_RMK(0),
           MCBSP_RCERE2_RMK(0),
           MCBSP_RCERE3_RMK(0),
#endif
           
#if (C64_SUPPORT)          
           MCBSP_XCERE0_RMK(0),       /* Additional registers only for 64x       */
           MCBSP_XCERE1_RMK(0),
           MCBSP_XCERE2_RMK(0),
           MCBSP_XCERE3_RMK(0),
#endif		   
		   
     MCBSP_PCR_RMK(
           MCBSP_PCR_XIOEN_SP,
           MCBSP_PCR_RIOEN_SP,
           MCBSP_PCR_FSXM_INTERNAL, /* frame sync generation               */
           MCBSP_PCR_FSRM_EXTERNAL, 
           MCBSP_PCR_CLKXM_OUTPUT,  /* tans. clock mode from internal SRGR */
           MCBSP_PCR_CLKRM_INPUT,
           MCBSP_PCR_CLKSSTAT_0,
           MCBSP_PCR_DXSTAT_0,
           MCBSP_PCR_FSXP_ACTIVELOW, /* active low trans. frame sync. polarity  */
           MCBSP_PCR_FSRP_ACTIVEHIGH,
           MCBSP_PCR_CLKXP_RISING,  /* trans. clk pol. from rising edge of CLKX */
           MCBSP_PCR_CLKRP_FALLING
           )
}; 

hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); /* McBSP port 0             */
MCBSP_config(hMcbsp0, &mcbspCfg0);
}

/*--------------------------------------------------------------------------------*/
/* set_interrupts_dma()                                                           */
/*--------------------------------------------------------------------------------*/
#if (DMA_SUPPORT)
void                           /* Set the interrupts         */
set_interrupts_dma(void)       /* if the device supports DMA */
{
 IRQ_nmiEnable();
 IRQ_globalEnable();
 IRQ_disable(IRQ_EVT_DMAINT2);
 IRQ_disable(IRQ_EVT_DMAINT1);  /* INT11 and INT9 */
 IRQ_clear(IRQ_EVT_DMAINT2);
 IRQ_clear(IRQ_EVT_DMAINT1);
 IRQ_enable(IRQ_EVT_DMAINT2);
 IRQ_enable(IRQ_EVT_DMAINT1);
 return;
}
#endif

/*--------------------------------------------------------------------------------*/
/* set_interrupts_edma()                                                          */
/*--------------------------------------------------------------------------------*/

#if (EDMA_SUPPORT)
void                          /* Set the interrupts          */
set_interrupts_edma(void)     /* if the device supports EDMA */
{
 IRQ_nmiEnable();
 IRQ_globalEnable();
 IRQ_reset(IRQ_EVT_EDMAINT);
 IRQ_disable(IRQ_EVT_EDMAINT);
 EDMA_intDisable(12);         /* ch 12 for McBSP transmit event XEVT0 */
 EDMA_intDisable(13);         /* ch 13 for McBSP receive event REVT0  */
 IRQ_clear(IRQ_EVT_EDMAINT);
 EDMA_intClear(12);
 EDMA_intClear(13);
 IRQ_enable(IRQ_EVT_EDMAINT);
 EDMA_intEnable(12);
 EDMA_intEnable(13);
  
 return;
}
#endif

/*--------------------------------------------------------------------------------*/
/*    DMA DATA TRANSFER COMPLETION ISRs                                           */
/*--------------------------------------------------------------------------------*/
interrupt void     /* vecs.asm hooks this up to IRQ 11 */
c_int11(void)      /* DMA ch2                          */
{
xmit0_done = TRUE;
return;
}

interrupt void       /* vecs.asm hooks this up to IRQ 09 */
c_int09(void)        /* DMA ch1                          */
{
recv0_done = TRUE;
return;
}

interrupt void    /* vecs.asm hooks this up to IRQ 08 */
c_int08(void)     /* for the EDMA                     */
{
 #if (EDMA_SUPPORT)   
  if (EDMA_intTest(12)) 
  {
  xmit0_done = TRUE;
  EDMA_intClear(12); /* clear CIPR bit so future interrupts can be recognized */
  }

  else if (EDMA_intTest(13)) 
  {
  recv0_done = TRUE;
  EDMA_intClear(13); /* clear CIPR bit so future interrupts can be recognized */
  }
#endif
return;
}
/*-----------------------End of spi_mode.c--------------------------------------*/