spi_mcbsp.c

ti_dsp_6000系列,开发环境ccs3.1 文件内容,与spi_rom的连接,用串口实现spi协议

/*---------------------------------------------------------------------------------*/
/* TI Proprietary Information                                                      */
/* 02/22/01: Vassos S. Soteriou                                                    */
/* spi_mode.c:                                                                     */
/* Tests SPI CLKSTP mode where CLKSTP=11b and CLKXP=0.  McBSP0 is the master.      */
/* Any other SPI-compliant device can be a slave.                                  */
/* This sample code transmits serial data from the McBSP to an SPI ROM, interrupts */
/* the CPU to inform completion of data transmit and then transmits the data from  */
/* the SPI ROM back to the McBSP and again interrupts the CPU to inform completion */ 
/* of the data receive.  The data is received/transmitted (initiated) using        */
/* either the DMA or EDMA depending on the type of the device used.  The transfer  */
/* size is determined by the xfer_size variable, and the buffer size (larger or    */
/* equal to the xfer_size) is determined by the BUFFER_SIZE variable. Default      */
/* values are 5 and 256 respectively in this sample code.                          */
/* In the case of a DMA transfer, the vecs.asm assembly code file is used to       */
/* hookup the c_int11() and c_int09() ISRs to the corresponding interrupts.        */
/* Channel 1 is hooked up to interrupt 9 for data receive, channel 2 is hooked up  */
/* to interrupt 11 for data transmit, the DMA controller has individual interrupts */
/* for each DMA channel.  The EDMA controller, however, generates a single         */
/* interrupt to the CPU (EDMA_INT) on behalf of all 16 channels (C621x/C671x) or   */
/* 64 channels (C64x). The various control registers and bit fields facilitate     */
/* EDMA interrupt generation.  CPU_INT8 is  responsible for all the EDMA channels  */
/* and the vecs.asm assembly file hooks up the c_int8 ISR to interrupt 8.          */
/* The program is based on CSL 2.0. Please refer to the TMS320C6000 Chip Support   */
/* Library API User's Guide for further information.                               */ 
/*---------------------------------------------------------------------------------*/
/* Chip definition, change this accordingly */
#define CHIP_6414 1

/* Inlcude files */
#include <c6x.h>
#include <csl.h>         /* CSL library   */
#include <csl_dma.h>     /* DMA_SUPPORT   */
#include <csl_edma.h>    /* EDMA_SUPPORT  */
#include <csl_irq.h>     /* IRQ_SUPPORT   */
#include <csl_mcbsp.h>   /* MCBSP_SUPPORT */

/*--------------------------------------------------------------------------------*/
/* Define constants */
#define FALSE 0
#define TRUE 1

#define DMA_SPI 8
#define XFER_SIZE 5         /* xfer_size less or equal to  BUFFER_SIZE  */
#define XFER_TYPE DMA_SPI

#define BUFFER_SIZE 256     /* change this to desired value             */

/* Global variables used in interrupt ISRs */
volatile int recv0_done = FALSE;
volatile int xmit0_done = FALSE;
/*--------------------------------------------------------------------------------*/
/* Declare CSL objects */

MCBSP_Handle hMcbsp0;       /* Handles for McBSP */

#if (DMA_SUPPORT)
DMA_Handle hDma1;           /* Handles for DMA   */
DMA_Handle hDma2;
#endif

#if (EDMA_SUPPORT)          /* Handles for EDMA  */
EDMA_Handle hEdma1;
EDMA_Handle hEdma2;
EDMA_Handle hEdmadummy;
#endif

/*--------------------------------------------------------------------------------*/
/* External functions and function prototypes */

void init_mcbsp0_master(void);   /* Function prototypes */
void set_interrupts_dma(void);
void set_interrupts_edma(void);

/* Inlcude the vector table to call the IRQ ISRs hookup */
extern far void vectors();

/*--------------------------------------------------------------------------------*/
/* main()                                                                         */
/*--------------------------------------------------------------------------------*/

void
main(void)
{
static int xfer_type;        /* Declaration of local variables */
static int xfer_size;

static Uint32 dmaInbuff[BUFFER_SIZE];   /* buffer for DMA supporting devices  */
static Uint32 dmaOutbuff[BUFFER_SIZE];
static Uint32 edmaInbuff[BUFFER_SIZE];  /* buffer for EDMA supporting devices */
static Uint32 edmaOutbuff[BUFFER_SIZE];

IRQ_setVecs(vectors); /* point to the IRQ vector table */

xfer_type = XFER_TYPE;
xfer_size = XFER_SIZE;

/* initialize the CSL library */
CSL_init();

init_mcbsp0_master();

/* Enable sample rate generator   GRST=1      */
MCBSP_enableSrgr(hMcbsp0);  /* Handle to SRGR */

switch (xfer_type) {
case DMA_SPI:

  #if (DMA_SUPPORT)       /* for DMA supporting devices */
  DMA_reset(INV);         /* reset all DMA channels     */
  #endif

  #if (EDMA_SUPPORT)           /* for EDMA supporting devices */
  EDMA_clearPram(0x00000000);  /* Clear PaRAM RAM of the EDMA */
  set_interrupts_edma();
  #endif

/*--------------------------------------------------------------------------------*/
/* DMA channels 1 and 2 config structures                                         */
/*--------------------------------------------------------------------------------*/

#if (DMA_SUPPORT)       /* for DMA supporting devices */   

  /* Channel 1 receives the data */
  hDma1 = DMA_open(DMA_CHA1, DMA_OPEN_RESET);  /* Handle to DMA channel 1 */
    DMA_configArgs(hDma1,
       DMA_PRICTL_RMK(
           DMA_PRICTL_DSTRLD_NONE,
           DMA_PRICTL_SRCRLD_NONE,
           DMA_PRICTL_EMOD_NOHALT,
           DMA_PRICTL_FS_DISABLE,
           DMA_PRICTL_TCINT_ENABLE, /* TCINT =1          */
           DMA_PRICTL_PRI_DMA,      /* DMA high priority */ 
           DMA_PRICTL_WSYNC_NONE,
           DMA_PRICTL_RSYNC_REVT0,  /* Set synchronization event REVT0=01101 */
           DMA_PRICTL_INDEX_NA,
           DMA_PRICTL_CNTRLD_NA,
           DMA_PRICTL_SPLIT_DISABLE,
           DMA_PRICTL_ESIZE_32BIT,  /* Element size 32 bits                  */
           DMA_PRICTL_DSTDIR_INC,   /* Increment destination by element size */
           DMA_PRICTL_SRCDIR_NONE,
           DMA_PRICTL_START_STOP
           ),
        DMA_SECCTL_RMK(
           DMA_SECCTL_WSPOL_NA,    /* only available for 6202 and 6203 devices */
           DMA_SECCTL_RSPOL_NA,    /* only available for 6202 and 6203 devices */
           DMA_SECCTL_FSIG_NA,     /* only available for 6202 and 6203 devices */
           DMA_SECCTL_DMACEN_LOW,
           DMA_SECCTL_WSYNCCLR_NOTHING,
           DMA_SECCTL_WSYNCSTAT_CLEAR,
           DMA_SECCTL_RSYNCCLR_NOTHING,
           DMA_SECCTL_RSYNCSTAT_CLEAR,
           DMA_SECCTL_WDROPIE_DISABLE,
           DMA_SECCTL_WDROPCOND_CLEAR,
           DMA_SECCTL_RDROPIE_DISABLE,
           DMA_SECCTL_RDROPCOND_CLEAR,
           DMA_SECCTL_BLOCKIE_ENABLE,   /* BLOCK IE=1 enables DMA channel int  */
           DMA_SECCTL_BLOCKCOND_CLEAR,
           DMA_SECCTL_LASTIE_DISABLE,
           DMA_SECCTL_LASTCOND_CLEAR,
           DMA_SECCTL_FRAMEIE_DISABLE,
           DMA_SECCTL_FRAMECOND_CLEAR,
           DMA_SECCTL_SXIE_DISABLE,
           DMA_SECCTL_SXCOND_CLEAR
           ),
        DMA_SRC_RMK(MCBSP_ADDRH(hMcbsp0, DRR)),
        DMA_DST_RMK((Uint32)dmaInbuff),
        DMA_XFRCNT_RMK(
           DMA_XFRCNT_FRMCNT_DEFAULT,
           DMA_XFRCNT_ELECNT_OF(xfer_size)
           )
);

  /* Channel 2 transmits the data */
  hDma2 = DMA_open(DMA_CHA2, DMA_OPEN_RESET);  /* Handle to DMA channel 2 */
    DMA_configArgs(hDma2,
       DMA_PRICTL_RMK(
           DMA_PRICTL_DSTRLD_NONE,
           DMA_PRICTL_SRCRLD_NONE,
           DMA_PRICTL_EMOD_NOHALT,
           DMA_PRICTL_FS_DISABLE,
           DMA_PRICTL_TCINT_ENABLE, /* TCINT =1                              */
           DMA_PRICTL_PRI_DMA,      /* DMA high priority                     */
           DMA_PRICTL_WSYNC_XEVT0,  /* Set synchronization event XEVT0=01100 */
           DMA_PRICTL_RSYNC_NONE,
           DMA_PRICTL_INDEX_NA,
           DMA_PRICTL_CNTRLD_NA,
           DMA_PRICTL_SPLIT_DISABLE,
           DMA_PRICTL_ESIZE_32BIT,  /* Element size 32 bits             */
           DMA_PRICTL_DSTDIR_NONE,
           DMA_PRICTL_SRCDIR_INC,   /* Increment source by element size */
           DMA_PRICTL_START_STOP
           ),
        DMA_SECCTL_RMK(
           DMA_SECCTL_WSPOL_NA,    /* only available for 6202 and 6203 devices */
           DMA_SECCTL_RSPOL_NA,    /* only available for 6202 and 6203 devices */
           DMA_SECCTL_FSIG_NA,     /* only available for 6202 and 6203 devices */
           DMA_SECCTL_DMACEN_LOW,
           DMA_SECCTL_WSYNCCLR_NOTHING,
           DMA_SECCTL_WSYNCSTAT_CLEAR,
           DMA_SECCTL_RSYNCCLR_NOTHING,
           DMA_SECCTL_RSYNCSTAT_CLEAR,
           DMA_SECCTL_WDROPIE_DISABLE,
           DMA_SECCTL_WDROPCOND_CLEAR,
           DMA_SECCTL_RDROPIE_DISABLE,
           DMA_SECCTL_RDROPCOND_CLEAR,
           DMA_SECCTL_BLOCKIE_ENABLE,    /* BLOCK IE=1 enables DMA channel int */
           DMA_SECCTL_BLOCKCOND_CLEAR,
           DMA_SECCTL_LASTIE_DISABLE,
           DMA_SECCTL_LASTCOND_CLEAR,
           DMA_SECCTL_FRAMEIE_DISABLE,
           DMA_SECCTL_FRAMECOND_CLEAR,
           DMA_SECCTL_SXIE_DISABLE,
           DMA_SECCTL_SXCOND_CLEAR
           ),
        DMA_SRC_RMK((Uint32)dmaOutbuff),
        DMA_DST_RMK(MCBSP_ADDRH(hMcbsp0, DXR)),
        DMA_XFRCNT_RMK(
           DMA_XFRCNT_FRMCNT_DEFAULT,
           DMA_XFRCNT_ELECNT_OF(xfer_size)
           )
); 

set_interrupts_dma(); /* initialize the interrupts                                   */
                      /* enable the interrupts after the DMA channels are opened as  */
                      /* the DMA_OPEN_RESET clears and disables the channel interrupt*/
                      /* once specified and clears the corresponding interrupt bits  */
                      /* in the IER. This is not applicable for the EDMA channel     */
                      /* open case                                                   */ 
DMA_start(hDma1);     /* Start DMA channels 1 and 2                                  */
DMA_start(hDma2);

#endif  /* end for dma supporting devices */

/*--------------------------------------------------------------------------------*/
/* EDMA channels 12 and 13 config structures                                      */
/*--------------------------------------------------------------------------------*/

  #if (EDMA_SUPPORT)      /* for EDMA supporting devices  */  
     
hEdma1 = EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET);
EDMA_configArgs(hEdma1,

#if (!C64_SUPPORT)     
     EDMA_OPT_RMK(
        EDMA_OPT_PRI_HIGH,       /* High priority EDMA   */
        EDMA_OPT_ESIZE_32BIT,    /* Element size 32 bits */
        EDMA_OPT_2DS_DEFAULT,
        EDMA_OPT_SUM_DEFAULT,
        EDMA_OPT_2DD_DEFAULT,
        EDMA_OPT_DUM_INC,        /* Destination increment by element size */
        EDMA_OPT_TCINT_YES,      /* Enable Transfer Complete Interrupt    */
        EDMA_OPT_TCC_OF(13),     /* TCCINT = 0xD, REVT0                   */
        EDMA_OPT_LINK_YES,       /* Enable linking to NULL table          */
        EDMA_OPT_FS_NO
        ),
#endif

#if (C64_SUPPORT)
     EDMA_OPT_RMK(
        EDMA_OPT_PRI_HIGH,       /* High priority EDMA   */
        EDMA_OPT_ESIZE_32BIT,    /* Element size 32 bits */
        EDMA_OPT_2DS_DEFAULT,
        EDMA_OPT_SUM_DEFAULT,
        EDMA_OPT_2DD_DEFAULT,
        EDMA_OPT_DUM_INC,        /* Destination increment by element size */
        EDMA_OPT_TCINT_YES,      /* Enable Transfer Complete Interrupt    */
        EDMA_OPT_TCC_OF(13),     /* TCCINT = 0xD, REVT0                   */
        EDMA_OPT_TCCM_DEFAULT,
        EDMA_OPT_ATCINT_DEFAULT,
        EDMA_OPT_ATCC_DEFAULT,
        EDMA_OPT_PDTS_DEFAULT,
        EDMA_OPT_PDTD_DEFAULT,
        EDMA_OPT_LINK_YES,       /* Enable linking to NULL table          */
        EDMA_OPT_FS_NO
        ),
#endif        

        EDMA_SRC_RMK(MCBSP_ADDRH(hMcbsp0, DRR)), /*src to DRR0                  */
        EDMA_CNT_RMK(0,xfer_size),               /*set count equal to xfer_size */
        EDMA_DST_RMK((Uint32)edmaInbuff),        /* dst addr to edmaInbuff      */
        EDMA_IDX_RMK(0,0),
        EDMA_RLD_RMK(0,0)
        );
  
  hEdma2 = EDMA_open(EDMA_CHA_XEVT0, EDMA_OPEN_RESET);
  EDMA_configArgs(hEdma2, 

#if(!C64_SUPPORT)
      EDMA_OPT_RMK(
        EDMA_OPT_PRI_HIGH,       /* High priority EDMA   */
        EDMA_OPT_ESIZE_32BIT,    /* Element size 32 bits */
        EDMA_OPT_2DS_DEFAULT,
        EDMA_OPT_SUM_INC,        /* Source increment by element size        */
        EDMA_OPT_2DD_DEFAULT,
        EDMA_OPT_DUM_DEFAULT,
        EDMA_OPT_TCINT_YES,      /* Enable Transfer Complete Interrupt      */
        EDMA_OPT_TCC_OF(12),     /* TCCINT = 0xC, XEVT0                     */
        EDMA_OPT_LINK_YES,       /* Enable linking to NULL table            */
        EDMA_OPT_FS_NO
        ),
#endif

#if(C64_SUPPORT)        
        EDMA_OPT_RMK(
        EDMA_OPT_PRI_HIGH,       /* High priority EDMA */
        EDMA_OPT_ESIZE_32BIT,    /* Element size 32 bits */
        EDMA_OPT_2DS_DEFAULT,
        EDMA_OPT_SUM_INC,        /* Source increment by element size        */
        EDMA_OPT_2DD_DEFAULT,
        EDMA_OPT_DUM_DEFAULT,
        EDMA_OPT_TCINT_YES,      /* Enable Transfer Complete Interrupt      */
        EDMA_OPT_TCC_OF(12),     /* TCCINT = 0xC, XEVT0                     */
        EDMA_OPT_TCCM_DEFAULT,