iekc64_ser.h

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/*
 *  Copyright 2002 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *  
 */
/* "@(#) RF5_IEK 2.00.02 12-11-02 (swat-c19)" */
/*! \verbatim
==============================================================================
                                  Copyright (C) 2002 A.T.E.M.E.
                          All Rights Reserved
------------------------------------------------------------------------------
 MODULE NAME... IEKC64_SERIAL
 FILENAME...... iekc64_ser.h
 PROJECT....... IEK C64x
------------------------------------------------------------------------------
 HISTORY:
 V1.0    09/01/2002  HCO 
         18/02/2002  HCO
------------------------------------------------------------------------------
\endverbatim <P> \file
 
        \brief Header file for the IEK C64 serial module.

</P>*//*====================================================================*/

#ifndef _SER_H_
#define _SER_H_

#include <csl_stdinc.h>
#include <csl_mcbsp.h>

#include "iekc64.h"
#include "iekc64_error.h"



#ifdef __cplusplus
extern "C" {
#endif

/*=======================================================================*//*!
\defgroup SER SER - Serial ports manager

        \brief This module provides a unified API for serial ports : RS232 and McBSP.

          The following paragraphs details the working of these two sub-modules
         
   <h3> MCBSP and UART module </h3>

        <b> How does it work </b>

                The SER - MCBSP module acquire frame according to the configuration defined 
                in IEKC64_SER structure.
                
        <b> Openning the module</b>
                
                You open the module by calling the SER_open() function. This function
                initialize the hardware and the software with the parameters given in the
                IEKC64_SER structure that you must fill before the call.
                For MCBSP, the parameter FALSE for ConfigMode means that you will used default
                configuration strucutre provided by the library.
                The default configuration structure field description is:
                
                <small>
                
                SPCR  =
                        \li MCBSP_SPCR_FREE_YES
                        \li MCBSP_SPCR_SOFT_NO
                        \li MCBSP_SPCR_FRST_NO
                        \li MCBSP_SPCR_GRST_NO
                        \li MCBSP_SPCR_XINTM_XRDY
                        \li MCBSP_SPCR_XSYNCERR_NO
                        \li MCBSP_SPCR_XRST_NO
                        \li MCBSP_SPCR_DLB_OFF
                        \li MCBSP_SPCR_RJUST_RZF
                        \li MCBSP_SPCR_CLKSTP_DISABLE
                        \li MCBSP_SPCR_DXENA_OFF
                        \li MCBSP_SPCR_RINTM_RRDY
                        \li MCBSP_SPCR_RSYNCERR_NO

                RCR   = 
                 
                        \li MCBSP_RCR_RPHASE_SINGLE
                        \li MCBSP_RCR_RFRLEN2_OF(0)
                        \li MCBSP_RCR_RWDLEN2_8BIT //Don't care about, we don't use phase
                        \li MCBSP_RCR_RCOMPAND_MSB
                        \li MCBSP_RCR_RFIG_YES
                        \li MCBSP_RCR_RDATDLY_1BIT
                        \li MCBSP_RCR_RFRLEN1_OF(0)
                        \li MCBSP_RCR_RWDLEN1_32BIT
                        \li MCBSP_RCR_RWDREVRS_DISABLE
                
                XCR   =
                        
                        \li MCBSP_XCR_XPHASE_SINGLE                              
                        \li MCBSP_XCR_XFRLEN2_OF(0)                                      
                        \li MCBSP_XCR_XWDLEN2_8BIT // Not using Phase 
                        \li MCBSP_XCR_XCOMPAND_MSB                                       
                        \li MCBSP_XCR_XFIG_YES                                   
                        \li MCBSP_XCR_XDATDLY_1BIT                                       
                        \li MCBSP_XCR_XFRLEN1_OF(0)                                      
                        \li MCBSP_XCR_XWDLEN1_32BIT                                      
                        \li MCBSP_XCR_XWDREVRS_DISABLE
                                     
                SRGR  =
                        
                        \li MCBSP_SRGR_GSYNC_FREE
                        \li MCBSP_SRGR_CLKSP_RISING                                      
                        \li MCBSP_SRGR_CLKSM_INTERNAL                                    
                        \li MCBSP_SRGR_FSGM_DXR2XSR                                      
                        \li MCBSP_SRGR_FPER_OF(0)                                        
                        \li MCBSP_SRGR_FWID_OF(0)                                        
                        \li MCBSP_SRGR_CLKGDV_OF(7)
                                         
                MCR   = MCBSP_MCR_OF(0)
                        
                RCERE0 = MCBSP_RCERE0_DEFAULT
                        
                RCERE1 = MCBSP_RCERE1_DEFAULT
                        
                RCERE2 = MCBSP_RCERE2_DEFAULT
                        
                RCERE3 = MCBSP_RCERE3_DEFAULT
                        
                XCERE0 = MCBSP_XCERE0_DEFAULT
                        
                XCERE1 = MCBSP_XCERE1_DEFAULT
                        
                XCERE2 = MCBSP_XCERE2_DEFAULT
                        
                XCERE3 = MCBSP_XCERE3_DEFAULT
                        
                PCR        =
                        
                        \li MCBSP_PCR_XIOEN_SP
                        \li MCBSP_PCR_RIOEN_SP
                        \li MCBSP_PCR_FSXM_INTERNAL
                        \li MCBSP_PCR_FSRM_EXTERNAL
                        \li MCBSP_PCR_CLKXM_OUTPUT
                        \li MCBSP_PCR_CLKRM_INPUT
                        \li MCBSP_PCR_CLKSSTAT_0
                        \li MCBSP_PCR_DXSTAT_0
                        \li MCBSP_PCR_FSXP_DEFAULT
                        \li MCBSP_PCR_FSRP_ACTIVEHIGH
                        \li MCBSP_PCR_CLKXP_RISING
                        \li MCBSP_PCR_CLKRP_FALLING
                        
                </small> 
                
        <b> Start serial acquisition/restitution </b>
        
                You start the module by calling the SER_start() function. This function
                start DMA and interrupt management.
                
        <b> Getting a frame</b>

                SER_receive() will give the next frame pointer from the input buffer.
                If no new frame is avalable, depending on the timeout value, you will
                get an error or wait until the timeout ends or a new frame is captured
        
        <b> Sending a frame</b>

                SER_send() will send the your current frame pointer to output.
                
        <b> Stop MCBSP </b>

                SER_stop() will allow the serial acquisition/restitution to be paused. After a 
                SER_stop, acquisition/restitution can be re-started with the same parameters 
                with SER_start().
        
        <b> Close MCBSP </b>

                SER_free() will close all channel and interupt used with the MCBSP serial communciation
                                        
   
</P>*//*==============================================================*//*@{*/


#define SER_MCBSP0      0x01
#define SER_MCBSP1      0x02
#define SER_MCBSP2      0x03
#define SER_RS232       0x04
#define SER_TI          0x05

#define SER_RS422       SER_MCBSP0
#define SER_UART        SER_RS232

/*--------------------------------------------------------------------------*/
/*! Defines the MCBSP configuration used for acquisition and restitution 
*/
typedef struct
{
    //! Serial port control register value
    Uint32 spcr;
        //! Receive control register value
        Uint32 rcr;
        //! Transmit control register value
        Uint32 xcr;
        //! Sample rate generator register value
        Uint32 srgr;
        //! Multichannel control register value
        Uint32 mcr;
        //! Enhanced receive channel 0 enable register value
        Uint32 rcere0;
        //! Enhanced receive channel 1 enable register value
        Uint32 rcere1;
        //! Enhanced receive channel 2 enable register value
        Uint32 rcere2;