iekc64.gel

来自「TI公司的算法标准 Framework5的源代码」· GEL 代码 · 共 143 行

StartUp()
{
        IEKC64x_Init(); 
        GEL_TextOut("IEKC64 Gel StartUp Complete.\n");
}

menuitem "ATEME's IEKC64x";


hotmenu IEKC64x_Init()
{
        GEL_Reset();
        map_Init(); 
        emif_Init();
        flush_Cache();
}

/*------------------------------------------------------------------------*/
/* EMIF registers definition                                                                                      */
/*------------------------------------------------------------------------*/
emif_Init()
{

#define C64_REGEMIFA_GBLCTL   *0x01800000
#define C64_REGEMIFA_CE0CTL   *0x01800008
#define C64_REGEMIFA_CE1CTL   *0x01800004
#define C64_REGEMIFA_CE2CTL   *0x01800010
#define C64_REGEMIFA_CE3CTL   *0x01800014
#define C64_REGEMIFA_CE0SEC   *0x01800048
#define C64_REGEMIFA_CE1SEC   *0x01800044
#define C64_REGEMIFA_CE2SEC   *0x01800050
#define C64_REGEMIFA_CE3SEC   *0x01800054
#define C64_REGEMIFA_SDCTL    *0x01800018
#define C64_REGEMIFA_SDTIM    *0x0180001C
#define C64_REGEMIFA_SDEXT    *0x01800020

#define C64_REGEMIFB_GBLCTL   *0x01A80000
#define C64_REGEMIFB_CE0CTL   *0x01A80008
#define C64_REGEMIFB_CE1CTL   *0x01A80004
#define C64_REGEMIFB_CE2CTL   *0x01A80010
#define C64_REGEMIFB_CE3CTL   *0x01A80014
#define C64_REGEMIFB_CE0SEC   *0x01A80048
#define C64_REGEMIFB_CE1SEC   *0x01A80044
#define C64_REGEMIFB_CE2SEC   *0x01A80050
#define C64_REGEMIFB_CE3SEC   *0x01A80054
#define C64_REGEMIFB_SDCTL    *0x01A80018
#define C64_REGEMIFB_SDTIM    *0x01A8001C
#define C64_REGEMIFB_SDEXT    *0x01A80020

  GEL_Reset();
 
  C64_REGEMIFA_GBLCTL = 0x000127A4;
  C64_REGEMIFA_CE0CTL = 0x000000D0;
  C64_REGEMIFA_CE1CTL = 0x31910811;
  C64_REGEMIFA_CE2CTL = 0x31910821;
  C64_REGEMIFA_CE3CTL = 0x00000040;
  C64_REGEMIFA_CE0SEC = 0;
  C64_REGEMIFA_CE1SEC = 0;
  C64_REGEMIFA_CE2SEC = 0;
  C64_REGEMIFA_CE3SEC = 0x00000060;
  C64_REGEMIFA_SDCTL  = 0x6A666000; 
  C64_REGEMIFA_SDTIM  = 0x0000061A;
  C64_REGEMIFA_SDEXT  = 0x0004B4A8;
  
  C64_REGEMIFB_GBLCTL = 0x000527A4;
  C64_REGEMIFB_CE0CTL = 0x00000090;
  C64_REGEMIFB_CE1CTL = 0x32530B01;
  C64_REGEMIFB_CE2CTL = 0x000000B0;
  C64_REGEMIFB_CE3CTL = 0x000000B0;
  C64_REGEMIFB_CE0SEC = 0;
  C64_REGEMIFB_CE1SEC = 0;
  C64_REGEMIFB_CE2SEC = 0x00000061;
  C64_REGEMIFB_CE3SEC = 0x00000000;
  C64_REGEMIFB_SDCTL  = 0x56666000;
  C64_REGEMIFB_SDTIM  = 0x0000030D;
  C64_REGEMIFB_SDEXT  = 0x0004B4A8;
  
  C64_REGEMIFB_SDCTL = (C64_REGEMIFB_SDCTL | (1 << 0x18));
  C64_REGEMIFA_SDCTL = (C64_REGEMIFA_SDCTL | (1 << 0x18));

}
  
/*------------------------------------------------------------------------*/
/* Setup the memory map for the IEKC64x board                                                     */
/*------------------------------------------------------------------------*/
map_Init()
{
  /* Enable memory mapping in Code Composer */
  GEL_MapOn();            

  /* Reset all memory to unreadable and unwritable */
  GEL_MapReset();         

  /* Syntax for GEL_MapAdd(address, page, length, readable, writeable)
   *    page:      Program Memory = 0, Data Memory = 1, I/O Space = 2
   *    readable:  Not Readable = 0,  Readable = 1
   *    writeable: Not Writeable = 0, Writeable = 1
   */

  /*---------------------------------------------------------------------*/
  /* IEKC64x specific memory mapping                                     */
  /*---------------------------------------------------------------------*/
   GEL_MapAdd(0x00000000,0,0x00000200,1,1); /* Reset and Interrupt Vector Table         */
   GEL_MapAdd(0x00000200,0,0x000001c0,1,1); /* Bootloader reserved space                */
   GEL_MapAdd(0x000003c0,0,0x00000040,1,1); /* PCI Communication Descriptor Tables      */
   GEL_MapAdd(0x00000400,0,0x000ffc00,1,1); /* DSP's on-chip memory                     */
   GEL_MapAdd(0x01800000,0,0x00000054,1,1); /* DSP internal registers*/         
   GEL_MapAdd(0x01A00000,0,0x000007FF,1,1); /* EDMA TABLE*/
   GEL_MapAdd(0x01A0FF9C,0,0x00000060,1,1); /* EDMA control register*/
   GEL_MapAdd(0x01A80000,0,0x00000054,1,1);
   GEL_MapAdd(0x01A40000,0,0x00001000,1,1);
   GEL_MapAdd(0x01C00000,0,0x00020008,1,1); /* PCI peripheral register                          */     
   GEL_MapAdd(0x60000000,0,0x00800000,1,1); /* External SDRAM EMIF B 8MB                */
   GEL_MapAdd(0x64000000,0,0x00200000,1,1); /* FLASH                                                    */
   GEL_MapAdd(0x68000000,0,0x00000001,1,1); /* video FIFO                                               */ 
   GEL_MapAdd(0x6C000000,0,0x00000001,1,1); /* Fast Port B FIFO                                 */ 
   GEL_MapAdd(0x80000000,0,0x10000000,1,1); /* External SDRAM EMIF A  256MB             */
   GEL_MapAdd(0x90000000,0,0x0000007F,1,1); /* Support logic                                    */
   GEL_MapAdd(0x90010000,0,0x0000007F,1,1); /* Support logic                                    */ 
   GEL_MapAdd(0x90040000,0,0x000000FF,1,1); /* EPLD                                                     */ 
   GEL_MapAdd(0x90080000,0,0x000000FF,1,1); /* FPGA                                                     */ 
   GEL_MapAdd(0x90200000,0,0x000001FF,1,1); /* Support logic                                    */ 
   GEL_MapAdd(0x90400000,0,0x0000007F,1,1); /* Fast Port A                                              */ 
   GEL_MapAdd(0x90600000,0,0x0000007F,1,1); /* Fast Port B                                              */ 
   GEL_MapAdd(0xA0000000,0,0x00400000,1,1); /* Cross Platform Interface CEA             */ 
   GEL_MapAdd(0xA0400000,0,0x00400000,1,1); /* Cross Platform Interface CEA             */ 
   GEL_MapAdd(0xB0000000,0,0x00000007,1,1); /* Fast Port A FIFO                                 */ 
   GEL_MapAdd(0x18C0000,0,0x03C,1,1);       /* Mcbsp0                                                           */
   GEL_MapAdd(0x1900000,0,0x03C,1,1);       /* Mcbsp1                                                           */
   GEL_MapAdd(0x1A40000,0,0x03C,1,1);       /* Mcbsp2                                                           */
}


/*------------------------------------------------------------------------*/
/* FlushCache()                                                                                                                   */
/* Actually Invalidate L1D and L1P, Internal RAM                                                  */
/*------------------------------------------------------------------------*/
flush_Cache()
{
        *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
        *(int *)0x01845000 = 0x1;
}