cfb_sp.tan.qmsg

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.

{ "Info" "ITAN_NO_REG2REG_EXIST" "CE " "Info: No valid register-to-register data paths exist for clock \"CE\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\] register PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[15\] 237.36 MHz 4.213 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 237.36 MHz between source register \"PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\]\" and destination register \"PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[15\]\" (period= 4.213 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.224 ns + Longest register register " "Info: + Longest register to register delay is 3.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\] 1 REG LCFF_X2_Y8_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y8_N3; Fanout = 3; REG Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.621 ns) 1.388 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\]~245 2 COMB LCCOMB_X2_Y8_N2 2 " "Info: 2: + IC(0.767 ns) + CELL(0.621 ns) = 1.388 ns; Loc. = LCCOMB_X2_Y8_N2; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\]~245'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.388 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1]~245 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.474 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[2\]~247 3 COMB LCCOMB_X2_Y8_N4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.474 ns; Loc. = LCCOMB_X2_Y8_N4; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[2\]~247'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1]~245 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[2]~247 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.560 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[3\]~249 4 COMB LCCOMB_X2_Y8_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.560 ns; Loc. = LCCOMB_X2_Y8_N6; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[3\]~249'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[2]~247 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[3]~249 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.646 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[4\]~251 5 COMB LCCOMB_X2_Y8_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.646 ns; Loc. = LCCOMB_X2_Y8_N8; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[4\]~251'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[3]~249 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[4]~251 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.732 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[5\]~253 6 COMB LCCOMB_X2_Y8_N10 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.732 ns; Loc. = LCCOMB_X2_Y8_N10; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[5\]~253'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[4]~251 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[5]~253 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.818 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[6\]~255 7 COMB LCCOMB_X2_Y8_N12 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.818 ns; Loc. = LCCOMB_X2_Y8_N12; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[6\]~255'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[5]~253 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[6]~255 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 2.008 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[7\]~257 8 COMB LCCOMB_X2_Y8_N14 2 " "Info: 8: + IC(0.000 ns) + CELL(0.190 ns) = 2.008 ns; Loc. = LCCOMB_X2_Y8_N14; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[7\]~257'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.190 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[6]~255 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[7]~257 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.094 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[8\]~259 9 COMB LCCOMB_X2_Y8_N16 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.094 ns; Loc. = LCCOMB_X2_Y8_N16; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[8\]~259'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[7]~257 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[8]~259 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.180 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[9\]~261 10 COMB LCCOMB_X2_Y8_N18 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.180 ns; Loc. = LCCOMB_X2_Y8_N18; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[9\]~261'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[8]~259 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[9]~261 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.266 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[10\]~263 11 COMB LCCOMB_X2_Y8_N20 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.266 ns; Loc. = LCCOMB_X2_Y8_N20; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[10\]~263'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[9]~261 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[10]~263 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.352 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[11\]~265 12 COMB LCCOMB_X2_Y8_N22 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.352 ns; Loc. = LCCOMB_X2_Y8_N22; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[11\]~265'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[10]~263 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[11]~265 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.438 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[12\]~267 13 COMB LCCOMB_X2_Y8_N24 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.438 ns; Loc. = LCCOMB_X2_Y8_N24; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[12\]~267'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[11]~265 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[12]~267 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.524 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[13\]~269 14 COMB LCCOMB_X2_Y8_N26 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.524 ns; Loc. = LCCOMB_X2_Y8_N26; Fanout = 2; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[13\]~269'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[12]~267 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[13]~269 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.610 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[14\]~271 15 COMB LCCOMB_X2_Y8_N28 1 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.610 ns; Loc. = LCCOMB_X2_Y8_N28; Fanout = 1; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[14\]~271'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.086 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[13]~269 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[14]~271 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.116 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[15\]~272 16 COMB LCCOMB_X2_Y8_N30 1 " "Info: 16: + IC(0.000 ns) + CELL(0.506 ns) = 3.116 ns; Loc. = LCCOMB_X2_Y8_N30; Fanout = 1; COMB Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[15\]~272'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.506 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[14]~271 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15]~272 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.224 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[15\] 17 REG LCFF_X2_Y8_N31 2 " "Info: 17: + IC(0.000 ns) + CELL(0.108 ns) = 3.224 ns; Loc. = LCFF_X2_Y8_N31; Fanout = 2; REG Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[15\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.108 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15]~272 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.457 ns ( 76.21 % ) " "Info: Total cell delay = 2.457 ns ( 76.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.767 ns ( 23.79 % ) " "Info: Total interconnect delay = 0.767 ns ( 23.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "3.224 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1]~245 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[2]~247 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[3]~249 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[4]~251 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[5]~253 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[6]~255 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[7]~257 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[8]~259 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[9]~261 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[10]~263 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[11]~265 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[12]~267 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[13]~269 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[14]~271 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15]~272 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.224 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1]~245 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[2]~247 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[3]~249 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[4]~251 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[5]~253 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[6]~255 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[7]~257 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[8]~259 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[9]~261 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[10]~263 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[11]~265 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[12]~267 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[13]~269 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[14]~271 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15]~272 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } { 0.000ns 0.767ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.725 ns - Smallest " "Info: - Smallest clock skew is -0.725 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.797 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.797 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CLK } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns CLK~clkctrl 2 COMB CLKCTRL_G1 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.970 ns) 3.110 ns F4:F4\|inst4 3 REG LCFF_X1_Y9_N21 4 " "Info: 3: + IC(0.871 ns) + CELL(0.970 ns) = 3.110 ns; Loc. = LCFF_X1_Y9_N21; Fanout = 4; REG Node = 'F4:F4\|inst4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.841 ns" { CLK~clkctrl F4:F4|inst4 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 208 264 328 288 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 3.503 ns F4:F4\|inst1 4 COMB LCCOMB_X1_Y9_N20 1 " "Info: 4: + IC(0.000 ns) + CELL(0.393 ns) = 3.503 ns; Loc. = LCCOMB_X1_Y9_N20; Fanout = 1; COMB Node = 'F4:F4\|inst1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.393 ns" { F4:F4|inst4 F4:F4|inst1 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { -8 824 888 40 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(0.000 ns) 4.241 ns F4:F4\|inst1~clkctrl 5 COMB CLKCTRL_G0 16 " "Info: 5: + IC(0.738 ns) + CELL(0.000 ns) = 4.241 ns; Loc. = CLKCTRL_G0; Fanout = 16; COMB Node = 'F4:F4\|inst1~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.738 ns" { F4:F4|inst1 F4:F4|inst1~clkctrl } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { -8 824 888 40 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 5.797 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[15\] 6 REG LCFF_X2_Y8_N31 2 " "Info: 6: + IC(0.890 ns) + CELL(0.666 ns) = 5.797 ns; Loc. = LCFF_X2_Y8_N31; Fanout = 2; REG Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[15\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.556 ns" { F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.159 ns ( 54.49 % ) " "Info: Total cell delay = 3.159 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.638 ns ( 45.51 % ) " "Info: Total interconnect delay = 2.638 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "5.797 ns" { CLK CLK~clkctrl F4:F4|inst4 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.797 ns" { CLK CLK~combout CLK~clkctrl F4:F4|inst4 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } { 0.000ns 0.000ns 0.139ns 0.871ns 0.000ns 0.738ns 0.890ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.393ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.522 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 6.522 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CLK } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns CLK~clkctrl 2 COMB CLKCTRL_G1 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.970 ns) 3.110 ns F4:F4\|inst6 3 REG LCFF_X1_Y9_N7 3 " "Info: 3: + IC(0.871 ns) + CELL(0.970 ns) = 3.110 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 3; REG Node = 'F4:F4\|inst6'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.841 ns" { CLK~clkctrl F4:F4|inst6 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 208 392 456 288 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.651 ns) 4.228 ns F4:F4\|inst1 4 COMB LCCOMB_X1_Y9_N20 1 " "Info: 4: + IC(0.467 ns) + CELL(0.651 ns) = 4.228 ns; Loc. = LCCOMB_X1_Y9_N20; Fanout = 1; COMB Node = 'F4:F4\|inst1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.118 ns" { F4:F4|inst6 F4:F4|inst1 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { -8 824 888 40 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(0.000 ns) 4.966 ns F4:F4\|inst1~clkctrl 5 COMB CLKCTRL_G0 16 " "Info: 5: + IC(0.738 ns) + CELL(0.000 ns) = 4.966 ns; Loc. = CLKCTRL_G0; Fanout = 16; COMB Node = 'F4:F4\|inst1~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.738 ns" { F4:F4|inst1 F4:F4|inst1~clkctrl } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { -8 824 888 40 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 6.522 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\] 6 REG LCFF_X2_Y8_N3 3 " "Info: 6: + IC(0.890 ns) + CELL(0.666 ns) = 6.522 ns; Loc. = LCFF_X2_Y8_N3; Fanout = 3; REG Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.556 ns" { F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.417 ns ( 52.39 % ) " "Info: Total cell delay = 3.417 ns ( 52.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.105 ns ( 47.61 % ) " "Info: Total interconnect delay = 3.105 ns ( 47.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "6.522 ns" { CLK CLK~clkctrl F4:F4|inst6 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.522 ns" { CLK CLK~combout CLK~clkctrl F4:F4|inst6 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] } { 0.000ns 0.000ns 0.139ns 0.871ns 0.467ns 0.738ns 0.890ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.651ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "5.797 ns" { CLK CLK~clkctrl F4:F4|inst4 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.797 ns" { CLK CLK~combout CLK~clkctrl F4:F4|inst4 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } { 0.000ns 0.000ns 0.139ns 0.871ns 0.000ns 0.738ns 0.890ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.393ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "6.522 ns" { CLK CLK~clkctrl F4:F4|inst6 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.522 ns" { CLK CLK~combout CLK~clkctrl F4:F4|inst6 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] } { 0.000ns 0.000ns 0.139ns 0.871ns 0.467ns 0.738ns 0.890ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.651ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "3.224 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1]~245 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[2]~247 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[3]~249 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[4]~251 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[5]~253 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[6]~255 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[7]~257 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[8]~259 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[9]~261 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[10]~263 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[11]~265 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[12]~267 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[13]~269 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[14]~271 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15]~272 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.224 ns" { PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1]~245 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[2]~247 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[3]~249 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[4]~251 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[5]~253 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[6]~255 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[7]~257 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[8]~259 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[9]~261 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[10]~263 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[11]~265 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[12]~267 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[13]~269 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[14]~271 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15]~272 PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } { 0.000ns 0.767ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "5.797 ns" { CLK CLK~clkctrl F4:F4|inst4 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.797 ns" { CLK CLK~combout CLK~clkctrl F4:F4|inst4 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[15] } { 0.000ns 0.000ns 0.139ns 0.871ns 0.000ns 0.738ns 0.890ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.393ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "6.522 ns" { CLK CLK~clkctrl F4:F4|inst6 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.522 ns" { CLK CLK~combout CLK~clkctrl F4:F4|inst6 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[1] } { 0.000ns 0.000ns 0.139ns 0.871ns 0.467ns 0.738ns 0.890ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.651ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "F4:F4\|inst4 INB CLK 4.575 ns register " "Info: tsu for register \"F4:F4\|inst4\" (data pin = \"INB\", clock pin = \"CLK\") is 4.575 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.421 ns + Longest pin register " "Info: + Longest pin to register delay is 7.421 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns INB 1 PIN PIN_6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_6; Fanout = 1; PIN Node = 'INB'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { INB } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.966 ns) + CELL(0.460 ns) 7.421 ns F4:F4\|inst4 2 REG LCFF_X1_Y9_N21 4 " "Info: 2: + IC(5.966 ns) + CELL(0.460 ns) = 7.421 ns; Loc. = LCFF_X1_Y9_N21; Fanout = 4; REG Node = 'F4:F4\|inst4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "6.426 ns" { INB F4:F4|inst4 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 208 264 328 288 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.455 ns ( 19.61 % ) " "Info: Total cell delay = 1.455 ns ( 19.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.966 ns ( 80.39 % ) " "Info: Total interconnect delay = 5.966 ns ( 80.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "7.421 ns" { INB F4:F4|inst4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.421 ns" { INB INB~combout F4:F4|inst4 } { 0.000ns 0.000ns 5.966ns } { 0.000ns 0.995ns 0.460ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 208 264 328 288 "inst4" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.806 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.806 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CLK } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns CLK~clkctrl 2 COMB CLKCTRL_G1 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.806 ns F4:F4\|inst4 3 REG LCFF_X1_Y9_N21 4 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.806 ns; Loc. = LCFF_X1_Y9_N21; Fanout = 4; REG Node = 'F4:F4\|inst4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.537 ns" { CLK~clkctrl F4:F4|inst4 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 208 264 328 288 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.796 ns ( 64.01 % ) " "Info: Total cell delay = 1.796 ns ( 64.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 35.99 % ) " "Info: Total interconnect delay = 1.010 ns ( 35.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "2.806 ns" { CLK CLK~clkctrl F4:F4|inst4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.806 ns" { CLK CLK~combout CLK~clkctrl F4:F4|inst4 } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.130ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "7.421 ns" { INB F4:F4|inst4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.421 ns" { INB INB~combout F4:F4|inst4 } { 0.000ns 0.000ns 5.966ns } { 0.000ns 0.995ns 0.460ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "2.806 ns" { CLK CLK~clkctrl F4:F4|inst4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.806 ns" { CLK CLK~combout CLK~clkctrl F4:F4|inst4 } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.130ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}