cfb_sp.tan.talkback.xml

来自「本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.」· XML 代码 · 共 108 行

<!--
This XML file (created on Wed Jun 14 15:16:25 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>000aeb14954f</host_id>
	<nic_id>000aeb14954f</nic_id>
	<cdrive_id>988e65e0</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Wed Jun 14 15:16:25 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows 2000</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1302</cpu_freq>
	</cpu>
	<ram units="MB">120</ram>
</machine>
<top_file>D:/altera/fpga+dsp/CFB_SP/CFB_SP</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off CFB_SP -c CFB_SP --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis is analyzing one or more combinational loops as latches</warning>
	<warning>Warning: Node &quot;F4:F4|inst26&quot; is a latch</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Wed Jun 14 15:16:24 2006</info>
	<info>Info: th for register &quot;PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0]&quot; (data pin = &quot;CLR&quot;, clock pin = &quot;CLK&quot;) is 3.759 ns</info>
	<info>Info: - Shortest pin to register delay is 3.069 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>CE</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>CLK</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>4.575 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>7.778 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tpd</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>5.560 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>3.759 ns</actual>
	</nonclk>
	<clk>
		<name>CLK</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>237.36 MHz ( period = 4.213 ns )</actual>
	</clk>
</performance>
<compile_id>5F940783</compile_id>
</talkback>