code_fd.hif

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.

Version 5.1 Build 176 10/26/2005 SJ Web Edition
10
727
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
LATCH1
# storage
db|Code_FD.(1).cnf
db|Code_FD.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LATCH1.v
5dabf57a58446e59464ea2fd176f568
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
pulse_count
# storage
db|Code_FD.(2).cnf
db|Code_FD.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pulse_count.v
e5bbd8d3341eeae9be2d6db81e861a8d
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
pulse_count:inst2
}
# end
# entity
F4
# storage
db|Code_FD.(3).cnf
db|Code_FD.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
F4.v
af445f5bbbf1fb6db7555ed01e6594
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
F4:inst1
}
# end
# entity
Code_FD
# storage
db|Code_FD.(0).cnf
db|Code_FD.(0).cnf
# case_insensitive
# source_file
Code_FD.bdf
5c4d8f173e0743f0218756cb750c1
23
# hierarchies {
|
}
# end
# complete