code_fd.map.qmsg

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.

{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[10\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[10\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[10\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[10\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[9\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[9\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[9\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[9\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[8\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[8\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[8\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[8\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[7\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[7\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[7\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[7\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[6\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[6\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[6\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[6\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[5\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[5\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[5\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[5\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[4\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[4\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[4\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[4\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[3\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[3\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[3\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[3\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[2\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[2\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[2\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[2\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[1\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[1\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[1\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[1\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[0\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[0\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[0\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[0\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[15\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[15\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[15\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[15\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[15\] GND " "Warning: Pin \"PULSE_COUNT\[15\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[14\] GND " "Warning: Pin \"PULSE_COUNT\[14\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[13\] GND " "Warning: Pin \"PULSE_COUNT\[13\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[12\] GND " "Warning: Pin \"PULSE_COUNT\[12\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[11\] GND " "Warning: Pin \"PULSE_COUNT\[11\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[10\] GND " "Warning: Pin \"PULSE_COUNT\[10\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[9\] GND " "Warning: Pin \"PULSE_COUNT\[9\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[8\] GND " "Warning: Pin \"PULSE_COUNT\[8\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[7\] GND " "Warning: Pin \"PULSE_COUNT\[7\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[6\] GND " "Warning: Pin \"PULSE_COUNT\[6\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[5\] GND " "Warning: Pin \"PULSE_COUNT\[5\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[4\] GND " "Warning: Pin \"PULSE_COUNT\[4\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[3\] GND " "Warning: Pin \"PULSE_COUNT\[3\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[2\] GND " "Warning: Pin \"PULSE_COUNT\[2\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[1\] GND " "Warning: Pin \"PULSE_COUNT\[1\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "PULSE_COUNT\[0\] GND " "Warning: Pin \"PULSE_COUNT\[0\]\" stuck at GND" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 480 687 48 "PULSE_COUNT\[15..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "4 " "Warning: Design contains 4 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "INA " "Warning: No output dependent on input pin \"INA\"" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 32 -184 -16 48 "INA" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CLR " "Warning: No output dependent on input pin \"CLR\"" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { -16 -184 -16 0 "CLR" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "INB " "Warning: No output dependent on input pin \"INB\"" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 64 -184 -16 80 "INB" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CLK " "Warning: No output dependent on input pin \"CLK\"" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 96 -184 -16 112 "CLK" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "20 " "Info: Implemented 20 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 62 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 62 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 13 17:10:09 2006 " "Info: Processing ended: Tue Jun 13 17:10:09 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}