pulse_count.fit.qmsg

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.

{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 31 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  31 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 35 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  35 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 36 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 36 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.137 ns register register " "Info: Estimated most critical path is register to register delay of 4.137 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PULSE_COUNT\[0\]~reg0 1 REG LAB_X1_Y3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y3; Fanout = 3; REG Node = 'PULSE_COUNT\[0\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[0]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.648 ns) + CELL(0.621 ns) 1.269 ns PULSE_COUNT\[0\]~243 2 COMB LAB_X1_Y3 2 " "Info: 2: + IC(0.648 ns) + CELL(0.621 ns) = 1.269 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[0\]~243'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "1.269 ns" { PULSE_COUNT[0]~reg0 PULSE_COUNT[0]~243 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 1.430 ns PULSE_COUNT\[1\]~245 3 COMB LAB_X1_Y3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.161 ns) = 1.430 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[1\]~245'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[0]~243 PULSE_COUNT[1]~245 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 1.591 ns PULSE_COUNT\[2\]~247 4 COMB LAB_X1_Y3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.161 ns) = 1.591 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[2\]~247'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[1]~245 PULSE_COUNT[2]~247 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 1.752 ns PULSE_COUNT\[3\]~249 5 COMB LAB_X1_Y3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.161 ns) = 1.752 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[3\]~249'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[2]~247 PULSE_COUNT[3]~249 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 1.913 ns PULSE_COUNT\[4\]~251 6 COMB LAB_X1_Y3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.161 ns) = 1.913 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[4\]~251'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[3]~249 PULSE_COUNT[4]~251 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 2.074 ns PULSE_COUNT\[5\]~253 7 COMB LAB_X1_Y3 2 " "Info: 7: + IC(0.000 ns) + CELL(0.161 ns) = 2.074 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[5\]~253'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[4]~251 PULSE_COUNT[5]~253 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 2.235 ns PULSE_COUNT\[6\]~255 8 COMB LAB_X1_Y3 2 " "Info: 8: + IC(0.000 ns) + CELL(0.161 ns) = 2.235 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[6\]~255'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[5]~253 PULSE_COUNT[6]~255 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 2.396 ns PULSE_COUNT\[7\]~257 9 COMB LAB_X1_Y3 2 " "Info: 9: + IC(0.000 ns) + CELL(0.161 ns) = 2.396 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[7\]~257'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[6]~255 PULSE_COUNT[7]~257 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 2.557 ns PULSE_COUNT\[8\]~259 10 COMB LAB_X1_Y3 2 " "Info: 10: + IC(0.000 ns) + CELL(0.161 ns) = 2.557 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[8\]~259'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[7]~257 PULSE_COUNT[8]~259 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 2.718 ns PULSE_COUNT\[9\]~261 11 COMB LAB_X1_Y3 2 " "Info: 11: + IC(0.000 ns) + CELL(0.161 ns) = 2.718 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[9\]~261'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[8]~259 PULSE_COUNT[9]~261 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 2.879 ns PULSE_COUNT\[10\]~263 12 COMB LAB_X1_Y3 2 " "Info: 12: + IC(0.000 ns) + CELL(0.161 ns) = 2.879 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[10\]~263'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[9]~261 PULSE_COUNT[10]~263 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 3.040 ns PULSE_COUNT\[11\]~265 13 COMB LAB_X1_Y3 2 " "Info: 13: + IC(0.000 ns) + CELL(0.161 ns) = 3.040 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[11\]~265'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[10]~263 PULSE_COUNT[11]~265 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 3.201 ns PULSE_COUNT\[12\]~267 14 COMB LAB_X1_Y3 2 " "Info: 14: + IC(0.000 ns) + CELL(0.161 ns) = 3.201 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[12\]~267'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[11]~265 PULSE_COUNT[12]~267 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 3.362 ns PULSE_COUNT\[13\]~269 15 COMB LAB_X1_Y3 2 " "Info: 15: + IC(0.000 ns) + CELL(0.161 ns) = 3.362 ns; Loc. = LAB_X1_Y3; Fanout = 2; COMB Node = 'PULSE_COUNT\[13\]~269'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[12]~267 PULSE_COUNT[13]~269 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 3.523 ns PULSE_COUNT\[14\]~271 16 COMB LAB_X1_Y3 1 " "Info: 16: + IC(0.000 ns) + CELL(0.161 ns) = 3.523 ns; Loc. = LAB_X1_Y3; Fanout = 1; COMB Node = 'PULSE_COUNT\[14\]~271'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.161 ns" { PULSE_COUNT[13]~269 PULSE_COUNT[14]~271 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.029 ns PULSE_COUNT\[15\]~272 17 COMB LAB_X1_Y3 1 " "Info: 17: + IC(0.000 ns) + CELL(0.506 ns) = 4.029 ns; Loc. = LAB_X1_Y3; Fanout = 1; COMB Node = 'PULSE_COUNT\[15\]~272'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.506 ns" { PULSE_COUNT[14]~271 PULSE_COUNT[15]~272 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.137 ns PULSE_COUNT\[15\]~reg0 18 REG LAB_X1_Y3 2 " "Info: 18: + IC(0.000 ns) + CELL(0.108 ns) = 4.137 ns; Loc. = LAB_X1_Y3; Fanout = 2; REG Node = 'PULSE_COUNT\[15\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.108 ns" { PULSE_COUNT[15]~272 PULSE_COUNT[15]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.489 ns ( 84.34 % ) " "Info: Total cell delay = 3.489 ns ( 84.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.648 ns ( 15.66 % ) " "Info: Total interconnect delay = 0.648 ns ( 15.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "4.137 ns" { PULSE_COUNT[0]~reg0 PULSE_COUNT[0]~243 PULSE_COUNT[1]~245 PULSE_COUNT[2]~247 PULSE_COUNT[3]~249 PULSE_COUNT[4]~251 PULSE_COUNT[5]~253 PULSE_COUNT[6]~255 PULSE_COUNT[7]~257 PULSE_COUNT[8]~259 PULSE_COUNT[9]~261 PULSE_COUNT[10]~263 PULSE_COUNT[11]~265 PULSE_COUNT[12]~267 PULSE_COUNT[13]~269 PULSE_COUNT[14]~271 PULSE_COUNT[15]~272 PULSE_COUNT[15]~reg0 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}