pulse_count.v

来自「本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.」· Verilog 代码 · 共 18 行

 module pulse_count(F4_CLK,RESET,DIRECTION,PULSE_COUNT);
   input F4_CLK,RESET,DIRECTION;
   output [15:0] PULSE_COUNT;
   reg [15:0] PULSE_COUNT;
   always @(posedge F4_CLK)
     begin
      if(RESET==1'b0)
       begin 
        if(DIRECTION==1'b1)
         PULSE_COUNT<=PULSE_COUNT+1;
        else
         PULSE_COUNT<=PULSE_COUNT-1;
       end
      else
        PULSE_COUNT<=24'b0;
     end 
 endmodule