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📄 pulse_count.fit.talkback.xml

📁 本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.
💻 XML
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		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load units="pF">0</load>
	</row>
	<row>
		<name>PULSE_COUNT[8]</name>
		<pin__>57</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>1</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load units="pF">0</load>
	</row>
	<row>
		<name>PULSE_COUNT[9]</name>
		<pin__>41</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>3</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load units="pF">0</load>
	</row>
</output_pins>
<i_o_bank_usage>
	<row>
		<i_o_bank>1</i_o_bank>
		<usage>20 / 34 ( 59 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>2</i_o_bank>
		<usage>0 / 35 ( 0 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>3</i_o_bank>
		<usage>1 / 37 ( 3 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>4</i_o_bank>
		<usage>1 / 36 ( 3 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
</i_o_bank_usage>
<advanced_data___general>
	<row>
		<name>Status Code</name>
		<value>0</value>
	</row>
	<row>
		<name>Desired User Slack</name>
		<value>0</value>
	</row>
	<row>
		<name>Fit Attempts</name>
		<value>1</value>
	</row>
</advanced_data___general>
<advanced_data___placement_preparation>
	<row>
		<name>Auto Fit Point 1 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>993990</value>
	</row>
	<row>
		<name>Internal Atom Count - Fit Attempt 1</name>
		<value>33</value>
	</row>
	<row>
		<name>LE/ALM Count - Fit Attempt 1</name>
		<value>17</value>
	</row>
	<row>
		<name>LAB Count - Fit Attempt 1</name>
		<value>2</value>
	</row>
	<row>
		<name>Outputs per Lab - Fit Attempt 1</name>
		<value>8.000</value>
	</row>
	<row>
		<name>Inputs per LAB - Fit Attempt 1</name>
		<value>1.000</value>
	</row>
	<row>
		<name>Global Inputs per LAB - Fit Attempt 1</name>
		<value>0.500</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global clock + sync load&apos; - Fit Attempt 1</name>
		<value>0:2</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global controls&apos; - Fit Attempt 1</name>
		<value>0:1;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global + aclr&apos; - Fit Attempt 1</name>
		<value>0:1;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global non-clock non-aclr&apos; - Fit Attempt 1</name>
		<value>0:2</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global controls&apos; - Fit Attempt 1</name>
		<value>0:1;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;deterministic LABSMUXA/LABXMUXB&apos; - Fit Attempt 1</name>
		<value>0:2</value>
	</row>
	<row>
		<name>LAB Constraint &apos;deterministic LABSMUXC/LABXMUXD&apos; - Fit Attempt 1</name>
		<value>0:1;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;clock / ce pair constraint&apos; - Fit Attempt 1</name>
		<value>0:1;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;aclr constraint&apos; - Fit Attempt 1</name>
		<value>0:1;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;true sload_sclear pair&apos; - Fit Attempt 1</name>
		<value>0:1;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;constant sload_sclear pair&apos; - Fit Attempt 1</name>
		<value>0:1;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;has placement constraint&apos; - Fit Attempt 1</name>
		<value>0:2</value>
	</row>
	<row>
		<name>LEs in Chains - Fit Attempt 1</name>
		<value>16</value>
	</row>
	<row>
		<name>LEs in Long Chains - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>LABs with Chains - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>LABs with Multiple Chains - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.020</value>
	</row>
</advanced_data___placement_preparation>
<advanced_data___placement>
	<row>
		<name>Auto Fit Point 2 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>995599</value>
	</row>
	<row>
		<name>Auto Fit Point 3 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>995599</value>
	</row>
	<row>
		<name>Auto Fit Point 4 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>995599</value>
	</row>
	<row>
		<name>Auto Fit Point 5 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.060</value>
	</row>
</advanced_data___placement>
<advanced_data___routing>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>995541</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Peak Regional Wire - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>995350</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>995350</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>995350</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.091</value>
	</row>
</advanced_data___routing>
<compilation_summary>
	<flow_status>Successful - Tue Jun 13 16:19:42 2006</flow_status>
	<quartus_ii_version>5.1 Build 176 10/26/2005 SJ Web Edition</quartus_ii_version>
	<revision_name>pulse_count</revision_name>
	<top_level_entity_name>pulse_count</top_level_entity_name>
	<family>Cyclone II</family>
	<device>EP2C5Q208C8</device>
	<timing_models>Preliminary</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>16 / 4,608 ( &lt; 1 % )</total_logic_elements>
	<total_registers>16</total_registers>
	<total_pins>19 / 142 ( 13 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>0 / 119,808 ( 0 % )</total_memory_bits>
	<embedded_multiplier_9_bit_elements>0 / 26 ( 0 % )</embedded_multiplier_9_bit_elements>
	<total_plls>0 / 2 ( 0 % )</total_plls>
</compilation_summary>
<compile_id>9E134A75</compile_id>
<files>
	<top>D:/altera/fpga+dsp/pusle_count/pulse_count.v</top>
	<extensions>
		<ext ext_name="v">1</ext>
		<ext ext_name="vwf">1</ext>
	</extensions>
	<sub_files>
		<sub_file>D:/altera/fpga+dsp/pusle_count/pulse_count.v</sub_file>
		<sub_file>D:/altera/fpga+dsp/pusle_count/pulse_count.vwf</sub_file>
	</sub_files>
</files>
<architecture>
	<family>Cyclone II</family>
	<auto_device>OFF</auto_device>
	<device>EP2C5Q208C8</device>
</architecture>
<pkg_io>
	<pin_std count="22">LVTTL</pin_std>
</pkg_io>
</talkback>

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