pulse_count.sim.talkback.xml

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.

<!--
This XML file (created on Tue Jun 13 16:20:29 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>000aeb14954f</host_id>
	<nic_id>000aeb14954f</nic_id>
	<cdrive_id>988e65e0</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_sim.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Tue Jun 13 16:20:30 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows 2000</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1302</cpu_freq>
	</cpu>
	<ram units="MB">120</ram>
</machine>
<top_file>D:/altera/fpga+dsp/pusle_count/pulse_count</top_file>
<mep_data>
	<command_line>quartus_sim --read_settings_files=on --write_settings_files=off pulse_count -c pulse_count</command_line>
</mep_data>
<messages>
	<info>Info: Quartus II Simulator was successful. 0 errors, 0 warnings</info>
	<info>Info: Elapsed time: 00:00:03</info>
	<info>Info: Processing ended: Tue Jun 13 16:20:29 2006</info>
	<info>Info: Number of transitions in simulation is 721</info>
	<info>Info: Simulation coverage is      70.15 %</info>
</messages>
<simulator_settings>
	<row>
		<option>Simulation mode</option>
		<setting>Timing</setting>
		<default_value>Timing</default_value>
	</row>
	<row>
		<option>Start time</option>
		<setting units="ns">0</setting>
		<default_value units="ns">0</default_value>
	</row>
	<row>
		<option>Add pins automatically to simulation output waveforms</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Check outputs</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Report simulation coverage</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Detect setup and hold time violations</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Detect glitches</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Automatically save/load simulation netlist</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Disable timing delays in Timing Simulation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Signal Activity File</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Group bus channels in simulation results</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer signal transitions to reduce memory requirements</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Overwrite Waveform Inputs With Simulation Outputs</option>
		<setting>Off</setting>
	</row>
</simulator_settings>
<simulator_summary>
	<simulation_start_time>0 ps</simulation_start_time>
	<simulation_end_time>50.0 us</simulation_end_time>
	<simulation_netlist_size>52 nodes</simulation_netlist_size>
	<simulation_coverage>     70.15 %</simulation_coverage>
	<total_number_of_transitions>721</total_number_of_transitions>
	<family>Cyclone II</family>
	<device>EP2C5Q208C8</device>
</simulator_summary>
<compile_id>64B2FA2C</compile_id>
</talkback>